*** Running vivado with args -log ngFEC_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ngFEC_top.tcl ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source ngFEC_top.tcl -notrace Command: synth_design -top ngFEC_top -part xcku115-flva2104-1-c Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xcku115' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcku115' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Device 21-403] Loading part xcku115-flva2104-1-c INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 7940 WARNING: [Synth 8-2507] parameter declaration becomes local in CrossClock_RX with formal parameter declaration list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v:42] WARNING: [Synth 8-2507] parameter declaration becomes local in rs_encoder_N15K13 with formal parameter declaration list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v:38] WARNING: [Synth 8-2507] parameter declaration becomes local in rs_encoder_N15K13 with formal parameter declaration list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v:39] WARNING: [Synth 8-2507] parameter declaration becomes local in rs_encoder_N15K13 with formal parameter declaration list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v:40] WARNING: [Synth 8-2507] parameter declaration becomes local in rs_encoder_N15K13 with formal parameter declaration list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v:41] WARNING: [Synth 8-2507] parameter declaration becomes local in rs_encoder_N15K13 with formal parameter declaration list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v:42] WARNING: [Synth 8-2507] parameter declaration becomes local in rs_encoder_N31K29 with formal parameter declaration list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v:39] WARNING: [Synth 8-2507] parameter declaration becomes local in rs_encoder_N31K29 with formal parameter declaration list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v:40] WARNING: [Synth 8-2507] parameter declaration becomes local in rs_encoder_N31K29 with formal parameter declaration list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v:41] WARNING: [Synth 8-2507] parameter declaration becomes local in rs_encoder_N31K29 with formal parameter declaration list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v:42] WARNING: [Synth 8-2507] parameter declaration becomes local in rs_encoder_N31K29 with formal parameter declaration list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v:43] WARNING: [Synth 8-6901] identifier 'sm_init' is used before its declaration [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_init.v:165] WARNING: [Synth 8-6901] identifier 'ST_TX_WAIT' is used before its declaration [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_init.v:165] WARNING: [Synth 8-6901] identifier 'sm_init' is used before its declaration [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_init.v:168] WARNING: [Synth 8-6901] identifier 'ST_RX_WAIT' is used before its declaration [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_init.v:168] --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1470.617 ; gain = 255.453 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'ngFEC_top' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:77] Parameter INITIAL_DELAY bound to: 50000000 - type: integer Parameter REFCLK_EN_TX_PATH bound to: 1'b0 Parameter REFCLK_HROW_CK_SEL bound to: 2'b00 Parameter REFCLK_ICNTL_RX bound to: 2'b00 INFO: [Synth 8-113] binding component instance 'i_GBT_refclk0_ibuf' to cell 'IBUFDS_GTE3' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:449] Parameter REFCLK_EN_TX_PATH bound to: 1'b0 Parameter REFCLK_HROW_CK_SEL bound to: 2'b00 Parameter REFCLK_ICNTL_RX bound to: 2'b00 INFO: [Synth 8-113] binding component instance 'i_GBT_refclk1_ibuf' to cell 'IBUFDS_GTE3' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:450] Parameter REFCLK_EN_TX_PATH bound to: 1'b0 Parameter REFCLK_HROW_CK_SEL bound to: 2'b00 Parameter REFCLK_ICNTL_RX bound to: 2'b00 INFO: [Synth 8-113] binding component instance 'i_GBT_refclk2_ibuf' to cell 'IBUFDS_GTE3' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:451] Parameter REFCLK_EN_TX_PATH bound to: 1'b0 Parameter REFCLK_HROW_CK_SEL bound to: 2'b00 Parameter REFCLK_ICNTL_RX bound to: 2'b00 INFO: [Synth 8-113] binding component instance 'i_GBT_refclk3_ibuf' to cell 'IBUFDS_GTE3' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:452] Parameter REFCLK_EN_TX_PATH bound to: 1'b0 Parameter REFCLK_HROW_CK_SEL bound to: 2'b00 Parameter REFCLK_ICNTL_RX bound to: 2'b00 INFO: [Synth 8-113] binding component instance 'i_refclk125_ibuf' to cell 'IBUFDS_GTE3' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:453] Parameter REFCLK_EN_TX_PATH bound to: 1'b0 Parameter REFCLK_HROW_CK_SEL bound to: 2'b00 Parameter REFCLK_ICNTL_RX bound to: 2'b00 INFO: [Synth 8-113] binding component instance 'i_TTC_rx_refclk_ibuf' to cell 'IBUFDS_GTE3' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:454] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double Parameter CLKOUT0_DIVIDE_F bound to: 20.000000 - type: double Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_DIVIDE bound to: 5 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double Parameter CLKOUT3_DIVIDE bound to: 4 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter CLKOUT4_CASCADE bound to: FALSE - type: string Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter IS_CLKFBIN_INVERTED bound to: 1'b0 Parameter IS_CLKIN1_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.010000 - type: double Parameter STARTUP_WAIT bound to: FALSE - type: string INFO: [Synth 8-113] binding component instance 'i_clk125_MMCM' to cell 'MMCME3_BASE' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:455] Parameter SIM_DEVICE bound to: ULTRASCALE - type: string Parameter STARTUP_SYNC bound to: FALSE - type: string INFO: [Synth 8-113] binding component instance 'i_refclk125_bufg' to cell 'BUFG_GT' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:477] INFO: [Synth 8-113] binding component instance 'i_clk125_bufg' to cell 'BUFG' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:478] INFO: [Synth 8-113] binding component instance 'i_clk200_bufg' to cell 'BUFG' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:479] INFO: [Synth 8-113] binding component instance 'i_clk250_bufg' to cell 'BUFG' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:480] INFO: [Synth 8-113] binding component instance 'i_DRPclk_bufg' to cell 'BUFG' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:481] INFO: [Synth 8-113] binding component instance 'i_ipb_clk_bufg' to cell 'BUFG' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:482] INFO: [Synth 8-3491] module 'axi_chip2chip_slave' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/axi_chip2chip64B66B_slave.vhd:37' bound to instance 'i_axi_slave' of component 'axi_chip2chip_slave' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:484] INFO: [Synth 8-638] synthesizing module 'axi_chip2chip_slave' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/axi_chip2chip64B66B_slave.vhd:56] INFO: [Synth 8-3491] module 'axi_chip2chip_64B66B' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/synth_1/.Xil/Vivado-15344-baby/realtime/axi_chip2chip_64B66B_stub.vhdl:5' bound to instance 'i_axi_chip2chip' of component 'axi_chip2chip_64B66B' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/axi_chip2chip64B66B_slave.vhd:192] INFO: [Synth 8-638] synthesizing module 'axi_chip2chip_64B66B' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/synth_1/.Xil/Vivado-15344-baby/realtime/axi_chip2chip_64B66B_stub.vhdl:61] INFO: [Synth 8-3491] module 'aurora_64b66b_0' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/synth_1/.Xil/Vivado-15344-baby/realtime/aurora_64b66b_0_stub.vhdl:5' bound to instance 'i_aurora' of component 'aurora_64b66b_0' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/axi_chip2chip64B66B_slave.vhd:260] INFO: [Synth 8-638] synthesizing module 'aurora_64b66b_0' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/synth_1/.Xil/Vivado-15344-baby/realtime/aurora_64b66b_0_stub.vhdl:46] INFO: [Synth 8-256] done synthesizing module 'axi_chip2chip_slave' (1#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/axi_chip2chip64B66B_slave.vhd:56] Parameter aclk_period bound to: 8 - type: integer INFO: [Synth 8-3491] module 'AXI4_to_ipbus' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/AXI4_to_ipbus_CCnew.vhd:41' bound to instance 'i_AXI4_to_ipbus' of component 'AXI4_to_ipbus' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:501] INFO: [Synth 8-638] synthesizing module 'AXI4_to_ipbus' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/AXI4_to_ipbus_CCnew.vhd:56] Parameter aclk_period bound to: 8 - type: integer Parameter N bound to: 32 - type: integer INFO: [Synth 8-3491] module 'srl_fiforeg' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:22' bound to instance 'i_w_FIFO' of component 'srl_fiforeg' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/AXI4_to_ipbus_CCnew.vhd:356] INFO: [Synth 8-638] synthesizing module 'srl_fiforeg' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:35] Parameter N bound to: 32 - type: integer Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] INFO: [Synth 8-256] done synthesizing module 'srl_fiforeg' (2#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:35] Parameter N bound to: 33 - type: integer INFO: [Synth 8-3491] module 'srl_fiforeg' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:22' bound to instance 'i_r_FIFO' of component 'srl_fiforeg' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/AXI4_to_ipbus_CCnew.vhd:367] INFO: [Synth 8-638] synthesizing module 'srl_fiforeg__parameterized1' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:35] Parameter N bound to: 33 - type: integer Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:42] INFO: [Synth 8-256] done synthesizing module 'srl_fiforeg__parameterized1' (2#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/srlfifo.vhd:35] INFO: [Synth 8-256] done synthesizing module 'AXI4_to_ipbus' (3#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/AXI4_to_ipbus_CCnew.vhd:56] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipbus_fabric.vhd:22] Parameter n_usr_slv bound to: 51 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric' (4#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipbus_fabric.vhd:22] Parameter sim bound to: 0 - type: bool INFO: [Synth 8-3491] module 'ipb_user_status_regs' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:40' bound to instance 'stat_regs_inst' of component 'ipb_user_status_regs' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:531] INFO: [Synth 8-638] synthesizing module 'ipb_user_status_regs' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:52] Parameter sim bound to: 0 - type: bool WARNING: [Synth 8-614] signal 'ipb_addr9_r' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:224] INFO: [Synth 8-3491] module 'cntr_rst_ctrl' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:36' bound to instance 'i_cntr_rst_ctrl' of component 'cntr_rst_ctrl' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:273] INFO: [Synth 8-638] synthesizing module 'cntr_rst_ctrl' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:46] Parameter INIT bound to: 32'b10010010010010010010010010010010 INFO: [Synth 8-113] binding component instance 'i_addr_p' to cell 'LUT5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:148] Parameter INIT bound to: 32'b10010010010010010010010010010010 INFO: [Synth 8-113] binding component instance 'i_reset_addr_p' to cell 'LUT5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:160] Parameter INIT bound to: 32'b00100100100100100100100100100100 INFO: [Synth 8-113] binding component instance 'i_addr_p' to cell 'LUT5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:148] Parameter INIT bound to: 32'b00100100100100100100100100100100 INFO: [Synth 8-113] binding component instance 'i_reset_addr_p' to cell 'LUT5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:160] Parameter INIT bound to: 32'b00111000111000111000111000111000 INFO: [Synth 8-113] binding component instance 'i_addr_p' to cell 'LUT5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:148] Parameter INIT bound to: 32'b00111000111000111000111000111000 INFO: [Synth 8-113] binding component instance 'i_reset_addr_p' to cell 'LUT5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:160] Parameter INIT bound to: 32'b11000000111111000000111111000000 INFO: [Synth 8-113] binding component instance 'i_addr_p' to cell 'LUT5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:148] Parameter INIT bound to: 32'b11000000111111000000111111000000 INFO: [Synth 8-113] binding component instance 'i_reset_addr_p' to cell 'LUT5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:160] Parameter INIT bound to: 32'b00000000111111111111000000000000 INFO: [Synth 8-113] binding component instance 'i_addr_p' to cell 'LUT5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:148] Parameter INIT bound to: 32'b00000000111111111111000000000000 INFO: [Synth 8-113] binding component instance 'i_reset_addr_p' to cell 'LUT5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:160] Parameter INIT bound to: 32'b11111111000000000000000000000000 INFO: [Synth 8-113] binding component instance 'i_addr_p' to cell 'LUT5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:148] Parameter INIT bound to: 32'b11111111000000000000000000000000 INFO: [Synth 8-113] binding component instance 'i_reset_addr_p' to cell 'LUT5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:160] Parameter INIT bound to: 32'b10100100100100100100100100100100 INFO: [Synth 8-113] binding component instance 'i_wraparound' to cell 'LUT5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:175] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-113] binding component instance 'DSP48E2_inst' to cell 'DSP48E2' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:247] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-113] binding component instance 'DSP48E2_inst' to cell 'DSP48E2' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:247] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-113] binding component instance 'DSP48E2_inst' to cell 'DSP48E2' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:247] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-113] binding component instance 'DSP48E2_inst' to cell 'DSP48E2' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:247] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-113] binding component instance 'DSP48E2_inst' to cell 'DSP48E2' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:247] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-113] binding component instance 'DSP48E2_inst' to cell 'DSP48E2' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:247] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-113] binding component instance 'DSP48E2_inst' to cell 'DSP48E2' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:247] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-113] binding component instance 'DSP48E2_inst' to cell 'DSP48E2' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:247] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-113] binding component instance 'DSP48E2_inst' to cell 'DSP48E2' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:247] INFO: [Common 17-14] Message 'Synth 8-113' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-256] done synthesizing module 'cntr_rst_ctrl' (5#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cntr_rst_ctrl.vhd:46] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-638] synthesizing module 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:42] Parameter ACASCREG bound to: 0 - type: integer Parameter ADREG bound to: 0 - type: integer Parameter ALUMODEREG bound to: 0 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 0 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 0 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 0 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 0 - type: integer Parameter CARRYINSELREG bound to: 0 - type: integer Parameter CREG bound to: 0 - type: integer Parameter DREG bound to: 0 - type: integer Parameter INMODEREG bound to: 0 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 0 - type: integer Parameter OPMODEREG bound to: 0 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 0 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: NONE - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP_MUX_b' (6#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:42] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-638] synthesizing module 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:43] Parameter ACASCREG bound to: 0 - type: integer Parameter ADREG bound to: 0 - type: integer Parameter ALUMODEREG bound to: 0 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 0 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 0 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 0 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 0 - type: integer Parameter CARRYINSELREG bound to: 0 - type: integer Parameter CREG bound to: 0 - type: integer Parameter DREG bound to: 0 - type: integer Parameter INMODEREG bound to: 0 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 0 - type: integer Parameter OPMODEREG bound to: 0 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 0 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: NONE - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP_MUX' (7#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:43] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX_b' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd:34' bound to instance 'i_DSP_MUX_b' of component 'DSP_MUX_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:289] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Synth 8-3491] module 'DSP_MUX' declared at 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd:34' bound to instance 'i_DSP_MUX' of component 'DSP_MUX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:297] INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter use_sync bound to: 4'b1111 INFO: [Synth 8-638] synthesizing module 'DSP_counterX4b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_counterX4b.vhd:41] Parameter use_sync bound to: 4'b1111 Parameter ACASCREG bound to: 0 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 0 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 0 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 0 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 0 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 0 - type: integer Parameter CARRYINSELREG bound to: 0 - type: integer Parameter CREG bound to: 0 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 0 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 0 - type: integer Parameter OPMODEREG bound to: 0 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: NONE - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: FOUR12 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 0 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 0 - type: integer Parameter CARRYINSELREG bound to: 0 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 0 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 0 - type: integer Parameter OPMODEREG bound to: 0 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 0 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: NONE - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: FOUR12 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (8#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'DSP_counterX4b' (9#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_counterX4b.vhd:41] Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 INFO: [Synth 8-638] synthesizing module 'DSP_MUX_C_b' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_C_b.vhd:44] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 0 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 0 - type: integer Parameter CARRYINSELREG bound to: 0 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 0 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 0 - type: integer Parameter OPMODEREG bound to: 0 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 0 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: NONE - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP_MUX_C_b' (10#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_C_b.vhd:44] INFO: [Synth 8-638] synthesizing module 'DSP_MUX_C' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_C.vhd:45] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 0 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 0 - type: integer Parameter CARRYINSELREG bound to: 0 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 0 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 0 - type: integer Parameter OPMODEREG bound to: 0 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 0 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: NONE - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP_MUX_C' (11#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_MUX_C.vhd:45] Parameter MEMORY_SIZE bound to: 16384 - type: integer Parameter MEMORY_PRIMITIVE bound to: block - type: string Parameter CLOCKING_MODE bound to: independent_clock - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: disable_sleep - type: string Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 00000000 - type: string Parameter READ_LATENCY_A bound to: 1 - type: integer Parameter WRITE_MODE_A bound to: no_change - type: string Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: no_change - type: string Parameter RST_MODE_B bound to: SYNC - type: string INFO: [Synth 8-6157] synthesizing module 'xpm_memory_tdpram' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8871] Parameter MEMORY_SIZE bound to: 16384 - type: integer Parameter MEMORY_PRIMITIVE bound to: block - type: string Parameter CLOCKING_MODE bound to: independent_clock - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: disable_sleep - type: string Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 00000000 - type: string Parameter READ_LATENCY_A bound to: 1 - type: integer Parameter WRITE_MODE_A bound to: no_change - type: string Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: no_change - type: string Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter P_CLOCKING_MODE bound to: 1 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 0 - type: integer Parameter P_WRITE_MODE_A bound to: 2 - type: integer Parameter P_WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_OPTIMIZATION bound to: 1 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 2 - type: integer Parameter MEMORY_SIZE bound to: 16384 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 00000000 - type: string Parameter READ_LATENCY_A bound to: 1 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: yes - type: string Parameter rsta_loop_iter bound to: 32 - type: integer Parameter rstb_loop_iter bound to: 32 - type: integer Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:490] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (12#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_tdpram' (13#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8871] Parameter ACASCREG bound to: 0 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 0 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 0 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 0 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 0 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 0 - type: integer Parameter CARRYINSELREG bound to: 0 - type: integer Parameter CREG bound to: 0 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 0 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 0 - type: integer Parameter OPMODEREG bound to: 0 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 0 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: NONE - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string Parameter use_sync bound to: 4'b1111 INFO: [Synth 8-638] synthesizing module 'DSP_counterX4' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_counterX4.vhd:41] Parameter use_sync bound to: 4'b1111 Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 0 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 0 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: NONE - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: FOUR12 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'DSP_counterX4' (14#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_counterX4.vhd:41] Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter use_sync bound to: 4'b1111 Parameter MEMORY_SIZE bound to: 16384 - type: integer Parameter MEMORY_PRIMITIVE bound to: block - type: string Parameter CLOCKING_MODE bound to: independent_clock - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: disable_sleep - type: string Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 00000000 - type: string Parameter READ_LATENCY_A bound to: 1 - type: integer Parameter WRITE_MODE_A bound to: no_change - type: string Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: no_change - type: string Parameter RST_MODE_B bound to: SYNC - type: string Parameter ACASCREG bound to: 0 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 0 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 0 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 0 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 0 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 0 - type: integer Parameter CARRYINSELREG bound to: 0 - type: integer Parameter CREG bound to: 0 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 0 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 0 - type: integer Parameter OPMODEREG bound to: 0 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 0 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: NONE - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string INFO: [Synth 8-256] done synthesizing module 'ipb_user_status_regs' (15#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_status_regsNew.vhd:52] INFO: [Synth 8-638] synthesizing module 'ipb_user_control_regs' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_control_regs.vhd:21] Parameter addr_width bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipb_user_control_regs' (16#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ipb_user_control_regs.vhd:21] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 18.000000 - type: double Parameter CLKFBOUT_PHASE bound to: 90.000000 - type: double Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string Parameter CLKIN1_PERIOD bound to: 24.950000 - type: double Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double Parameter CLKOUT0_DIVIDE_F bound to: 18.000000 - type: double Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT1_DIVIDE bound to: 6 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT4_CASCADE bound to: FALSE - type: string Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string Parameter COMPENSATION bound to: AUTO - type: string Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter IS_CLKFBIN_INVERTED bound to: 1'b0 Parameter IS_CLKIN1_INVERTED bound to: 1'b0 Parameter IS_CLKIN2_INVERTED bound to: 1'b0 Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 Parameter IS_PSEN_INVERTED bound to: 1'b0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.010000 - type: double Parameter REF_JITTER2 bound to: 0.010000 - type: double Parameter SS_EN bound to: FALSE - type: string Parameter SS_MODE bound to: CENTER_HIGH - type: string Parameter SS_MOD_PERIOD bound to: 10000 - type: integer Parameter STARTUP_WAIT bound to: FALSE - type: string Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 INFO: [Synth 8-638] synthesizing module 'DSP_dividerX3' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX3.vhd:47] Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: RESET_MATCH - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 0 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b111111111111111111111111111111111000000000000000 Parameter MREG bound to: 0 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: NONE - type: string Parameter USE_PATTERN_DETECT bound to: PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'DSP_dividerX3' (17#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX3.vhd:47] Parameter use_sync bound to: 3'b111 INFO: [Synth 8-638] synthesizing module 'DSP_rate_counterX3' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_rate_counterX3.vhd:42] Parameter use_sync bound to: 3'b111 Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 0 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 Parameter MREG bound to: 0 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: NONE - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'DSP_rate_counterX3' (18#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_rate_counterX3.vhd:42] Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 INFO: [Synth 8-638] synthesizing module 'DSP_dividerX2' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:48] Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AMULTSEL bound to: A - type: string Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: RESET_MATCH - type: string Parameter AUTORESET_PRIORITY bound to: RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BMULTSEL bound to: B - type: string Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 0 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 Parameter IS_RSTA_INVERTED bound to: 1'b0 Parameter IS_RSTB_INVERTED bound to: 1'b0 Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 Parameter IS_RSTC_INVERTED bound to: 1'b0 Parameter IS_RSTD_INVERTED bound to: 1'b0 Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 Parameter IS_RSTM_INVERTED bound to: 1'b0 Parameter IS_RSTP_INVERTED bound to: 1'b0 Parameter MASK bound to: 48'b111111111111111111111111111111111000000000000000 Parameter MREG bound to: 0 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREADDINSEL bound to: A - type: string Parameter PREG bound to: 1 - type: integer Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_MULT bound to: NONE - type: string Parameter USE_PATTERN_DETECT bound to: PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Parameter USE_WIDEXOR bound to: FALSE - type: string Parameter XORSIMD bound to: XOR24_48_96 - type: string Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'DSP_dividerX2' (19#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:48] Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter use_sync bound to: 3'b111 Parameter pattern bound to: 16'b0000000000000000 Parameter mask bound to: 16'b1000000000000000 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 3'b111 Parameter use_sync bound to: 2'b11 Parameter pattern bound to: 24'b000000000000000000000000 Parameter mask bound to: 24'b111111111000000000000000 Parameter SIM bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'TCDS2_if' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/TCDS2_if.vhd:71] Parameter SIM bound to: 0 - type: bool Parameter SIM bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'ttc_mgt_wrapper' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_wrapper.vhd:64] Parameter SIM bound to: 0 - type: bool Parameter REFCLK_EN_TX_PATH bound to: 1'b1 Parameter REFCLK_ICNTL_TX bound to: 5'b00111 INFO: [Synth 8-6157] synthesizing module 'ttc_mgt_example_gtwiz_userclk_tx' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_userclk_tx.v:60] Parameter P_CONTENTS bound to: 0 - type: integer Parameter P_FREQ_RATIO_SOURCE_TO_USRCLK bound to: 1 - type: integer Parameter P_FREQ_RATIO_USRCLK_TO_USRCLK2 bound to: 1 - type: integer Parameter P_USRCLK_INT_DIV bound to: 0 - type: integer Parameter P_USRCLK_DIV bound to: 3'b000 Parameter P_USRCLK2_INT_DIV bound to: 0 - type: integer Parameter P_USRCLK2_DIV bound to: 3'b000 INFO: [Synth 8-6157] synthesizing module 'BUFG_GT' [D:/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1259] Parameter SIM_DEVICE bound to: ULTRASCALE - type: string Parameter STARTUP_SYNC bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'BUFG_GT' (20#1) [D:/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1259] INFO: [Synth 8-6155] done synthesizing module 'ttc_mgt_example_gtwiz_userclk_tx' (21#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_userclk_tx.v:60] INFO: [Synth 8-6157] synthesizing module 'ttc_mgt_example_gtwiz_userclk_rx' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_userclk_rx.v:60] Parameter P_CONTENTS bound to: 0 - type: integer Parameter P_FREQ_RATIO_SOURCE_TO_USRCLK bound to: 1 - type: integer Parameter P_FREQ_RATIO_USRCLK_TO_USRCLK2 bound to: 1 - type: integer Parameter P_USRCLK_INT_DIV bound to: 0 - type: integer Parameter P_USRCLK_DIV bound to: 3'b000 Parameter P_USRCLK2_INT_DIV bound to: 0 - type: integer Parameter P_USRCLK2_DIV bound to: 3'b000 INFO: [Synth 8-6155] done synthesizing module 'ttc_mgt_example_gtwiz_userclk_rx' (22#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_userclk_rx.v:60] Parameter SIM bound to: 0 - type: bool INFO: [Synth 8-6157] synthesizing module 'ttc_mgt_example_init' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_init.v:59] Parameter P_FREERUN_FREQUENCY bound to: 125.000000 - type: double Parameter SIM bound to: 0 - type: bool Parameter P_TX_TIMER_DURATION_US bound to: 30000.000000 - type: double Parameter P_RX_TIMER_DURATION_US bound to: 130000.000000 - type: double Parameter P_TX_TIMER_DURATION_US_SIM bound to: 10.000000 - type: double Parameter P_RX_TIMER_DURATION_US_SIM bound to: 50.000000 - type: double Parameter ST_START bound to: 2'b00 Parameter ST_TX_WAIT bound to: 2'b01 Parameter ST_RX_WAIT bound to: 2'b10 Parameter ST_MONITOR bound to: 2'b11 INFO: [Synth 8-6157] synthesizing module 'ttc_mgt_example_reset_synchronizer' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_reset_sync.v:58] Parameter FREQUENCY bound to: 512 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ttc_mgt_example_reset_synchronizer' (23#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_reset_sync.v:58] INFO: [Synth 8-6157] synthesizing module 'ttc_mgt_example_bit_synchronizer' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_bit_sync.v:58] Parameter INITIALIZE bound to: 5'b00000 Parameter FREQUENCY bound to: 512 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ttc_mgt_example_bit_synchronizer' (24#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_bit_sync.v:58] INFO: [Synth 8-6155] done synthesizing module 'ttc_mgt_example_init' (25#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_init.v:59] INFO: [Synth 8-6157] synthesizing module 'ttc_mgt_example_gtwiz_reset' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_reset.v:60] Parameter P_FREERUN_FREQUENCY bound to: 125.000000 - type: double Parameter P_USE_CPLL_CAL bound to: 0 - type: integer Parameter P_TX_PLL_TYPE bound to: 0 - type: integer Parameter P_RX_PLL_TYPE bound to: 1 - type: integer Parameter P_RX_LINE_RATE bound to: 10.260224 - type: double Parameter P_CDR_TIMEOUT_FREERUN_CYC bound to: 26'b00000001101110000011010010 Parameter ST_RESET_ALL_INIT bound to: 3'b000 Parameter ST_RESET_ALL_BRANCH bound to: 3'b001 Parameter ST_RESET_ALL_TX_PLL bound to: 3'b010 Parameter ST_RESET_ALL_TX_PLL_WAIT bound to: 3'b011 Parameter ST_RESET_ALL_RX_DP bound to: 3'b100 Parameter ST_RESET_ALL_RX_PLL bound to: 3'b101 Parameter ST_RESET_ALL_RX_WAIT bound to: 3'b110 Parameter ST_RESET_ALL_DONE bound to: 3'b111 Parameter P_TX_PLL_RESET_FREERUN_CYC bound to: 10'b0000000111 Parameter ST_RESET_TX_BRANCH bound to: 3'b000 Parameter ST_RESET_TX_PLL bound to: 3'b001 Parameter ST_RESET_TX_DATAPATH bound to: 3'b010 Parameter ST_RESET_TX_WAIT_LOCK bound to: 3'b011 Parameter ST_RESET_TX_WAIT_USERRDY bound to: 3'b100 Parameter ST_RESET_TX_WAIT_RESETDONE bound to: 3'b101 Parameter ST_RESET_TX_IDLE bound to: 3'b110 Parameter P_RX_PLL_RESET_FREERUN_CYC bound to: 10'b0011111100 Parameter ST_RESET_RX_BRANCH bound to: 3'b000 Parameter ST_RESET_RX_PLL bound to: 3'b001 Parameter ST_RESET_RX_DATAPATH bound to: 3'b010 Parameter ST_RESET_RX_WAIT_LOCK bound to: 3'b011 Parameter ST_RESET_RX_WAIT_CDR bound to: 3'b100 Parameter ST_RESET_RX_WAIT_USERRDY bound to: 3'b101 Parameter ST_RESET_RX_WAIT_RESETDONE bound to: 3'b110 Parameter ST_RESET_RX_IDLE bound to: 3'b111 INFO: [Synth 8-155] case statement is not full and has no default [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_reset.v:171] INFO: [Synth 8-6157] synthesizing module 'ttc_mgt_example_reset_inv_synchronizer' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_reset_inv_sync.v:58] Parameter FREQUENCY bound to: 512 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ttc_mgt_example_reset_inv_synchronizer' (26#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_reset_inv_sync.v:58] INFO: [Synth 8-6155] done synthesizing module 'ttc_mgt_example_gtwiz_reset' (27#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_reset.v:60] INFO: [Synth 8-638] synthesizing module 'ttc_mgt' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/synth_1/.Xil/Vivado-15344-baby/realtime/ttc_mgt_stub.vhdl:64] INFO: [Synth 8-256] done synthesizing module 'ttc_mgt_wrapper' (28#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/ttc_mgt_wrapper.vhd:64] INFO: [Synth 8-638] synthesizing module 'prbs_gen' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/hprbs_framing/prbs_gen.vhd:90] Parameter g_PARAL_FACTOR bound to: 234 - type: integer Parameter g_PRBS_POLYNOMIAL bound to: 24'b100001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'prbs_gen' (29#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/hprbs_framing/prbs_gen.vhd:90] INFO: [Synth 8-638] synthesizing module 'prbs_chk' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/hprbs_framing/prbs_chk.vhd:92] Parameter g_GOOD_FRAME_TO_LOCK bound to: 15 - type: integer Parameter g_BAD_FRAME_TO_UNLOCK bound to: 5 - type: integer Parameter g_PARAL_FACTOR bound to: 234 - type: integer Parameter g_PRBS_POLYNOMIAL bound to: 24'b100001000000000000000001 Parameter g_PARAL_FACTOR bound to: 234 - type: integer Parameter g_PRBS_POLYNOMIAL bound to: 24'b100001000000000000000001 INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/hprbs_framing/prbs_chk.vhd:180] INFO: [Synth 8-256] done synthesizing module 'prbs_chk' (30#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/hprbs_framing/prbs_chk.vhd:92] INFO: [Synth 8-638] synthesizing module 'unlock_counter' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cms-tcds2-firmware-master/components/counters/firmware/hdl/unlock_counter.vhd:31] Parameter G_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'unlock_counter' (31#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cms-tcds2-firmware-master/components/counters/firmware/hdl/unlock_counter.vhd:31] INFO: [Synth 8-638] synthesizing module 'ttc2_frame_splitter' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cms-tcds2-firmware-master/components/tcds2_link/firmware/hdl/ttc2_frame_splitter.vhd:39] Parameter G_LINK_SPEED bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'ttc2_frame_splitter' (32#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cms-tcds2-firmware-master/components/tcds2_link/firmware/hdl/ttc2_frame_splitter.vhd:39] INFO: [Synth 8-638] synthesizing module 'tts2_frame_builder' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cms-tcds2-firmware-master/components/tcds2_link/firmware/hdl/tts2_frame_builder.vhd:39] Parameter G_LINK_SPEED bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'tts2_frame_builder' (33#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/cms-tcds2-firmware-master/components/tcds2_link/firmware/hdl/tts2_frame_builder.vhd:39] INFO: [Synth 8-638] synthesizing module 'lpgbtfpga_uplink_fixed' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/lpgbtfpga_uplink_fixed.vhd:91] Parameter DATARATE bound to: 2 - type: integer Parameter FEC bound to: 1 - type: integer Parameter c_multicyleDelay bound to: 3 - type: integer Parameter c_clockRatio bound to: 8 - type: integer Parameter c_mgtWordWidth bound to: 32 - type: integer Parameter c_allowedFalseHeader bound to: 5 - type: integer Parameter c_allowedFalseHeaderOverN bound to: 64 - type: integer Parameter c_requiredTrueHeader bound to: 32 - type: integer Parameter c_bitslip_mindly bound to: 2 - type: integer Parameter c_bitslip_waitdly bound to: 40 - type: integer Parameter c_resetOnEven bound to: 1 - type: integer Parameter c_resetDuration bound to: 10 - type: integer Parameter c_wordRatio bound to: 8 - type: integer Parameter c_wordSize bound to: 32 - type: integer Parameter c_headerPattern bound to: 2'b01 Parameter c_allowedFalseHeader bound to: 5 - type: integer Parameter c_allowedFalseHeaderOverN bound to: 64 - type: integer Parameter c_requiredTrueHeader bound to: 32 - type: integer Parameter c_resetOnEven bound to: 1 - type: integer Parameter c_resetDuration bound to: 10 - type: integer Parameter c_bitslip_mindly bound to: 2 - type: integer Parameter c_bitslip_waitdly bound to: 40 - type: integer INFO: [Synth 8-638] synthesizing module 'lpgbtfpga_framealigner' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_framealigner.vhd:64] Parameter c_wordRatio bound to: 8 - type: integer Parameter c_wordSize bound to: 32 - type: integer Parameter c_headerPattern bound to: 2'b01 Parameter c_allowedFalseHeader bound to: 5 - type: integer Parameter c_allowedFalseHeaderOverN bound to: 64 - type: integer Parameter c_requiredTrueHeader bound to: 32 - type: integer Parameter c_alignementMode bound to: 0 - type: integer Parameter c_resetOnEven bound to: 1 - type: integer Parameter c_resetDuration bound to: 10 - type: integer Parameter c_bitslip_mindly bound to: 2 - type: integer Parameter c_bitslip_waitdly bound to: 40 - type: integer Parameter INITIALIZE bound to: 5'b00000 INFO: [Synth 8-638] synthesizing module 'bit_synchronizer' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/common/bit_synchronizer.vhd:75] Parameter INITIALIZE bound to: 5'b00000 INFO: [Synth 8-256] done synthesizing module 'bit_synchronizer' (34#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/common/bit_synchronizer.vhd:75] Parameter INITIALIZE bound to: 5'b00000 Parameter INITIALIZE bound to: 5'b00000 INFO: [Synth 8-256] done synthesizing module 'lpgbtfpga_framealigner' (35#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_framealigner.vhd:64] Parameter c_clockRatio bound to: 8 - type: integer Parameter c_inputWidth bound to: 32 - type: integer Parameter c_outputWidth bound to: 256 - type: integer Parameter c_counterInitValue bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'lpgbtfpga_rxGearbox' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_rxgearbox.vhd:51] Parameter c_clockRatio bound to: 8 - type: integer Parameter c_inputWidth bound to: 32 - type: integer Parameter c_outputWidth bound to: 256 - type: integer Parameter c_counterInitValue bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'lpgbtfpga_rxGearbox' (36#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_rxgearbox.vhd:51] Parameter DATARATE bound to: 2 - type: integer Parameter FEC bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'lpgbtfpga_deinterleaver' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_deinterleaver.vhd:43] Parameter DATARATE bound to: 2 - type: integer Parameter FEC bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'lpgbtfpga_deinterleaver' (37#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_deinterleaver.vhd:43] Parameter DATARATE bound to: 2 - type: integer Parameter FEC bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'lpgbtfpga_decoder' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_decoder.vhd:51] Parameter DATARATE bound to: 2 - type: integer Parameter FEC bound to: 1 - type: integer Parameter N bound to: 31 - type: integer Parameter K bound to: 29 - type: integer Parameter SYMB_BITWIDTH bound to: 5 - type: integer INFO: [Synth 8-638] synthesizing module 'rs_decoder_N31K29' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/fec_rsDecoderN31K29.vhd:31] Parameter N bound to: 31 - type: integer Parameter K bound to: 29 - type: integer Parameter SYMB_BITWIDTH bound to: 5 - type: integer INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/fec_rsDecoderN31K29.vhd:72] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/fec_rsDecoderN31K29.vhd:119] INFO: [Synth 8-256] done synthesizing module 'rs_decoder_N31K29' (38#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/fec_rsDecoderN31K29.vhd:31] Parameter N bound to: 31 - type: integer Parameter K bound to: 29 - type: integer Parameter SYMB_BITWIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'lpgbtfpga_decoder' (39#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_decoder.vhd:51] Parameter FEC bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'lpgbtfpga_descrambler' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_descrambler.vhd:45] Parameter FEC bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'descrambler58bitOrder58' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/descrambler_58bitOrder58.vhd:34] INFO: [Synth 8-256] done synthesizing module 'descrambler58bitOrder58' (40#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/descrambler_58bitOrder58.vhd:34] INFO: [Synth 8-638] synthesizing module 'descrambler60bitOrder58' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/descrambler_60bitOrder58.vhd:34] INFO: [Synth 8-256] done synthesizing module 'descrambler60bitOrder58' (41#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/descrambler_60bitOrder58.vhd:34] INFO: [Synth 8-256] done synthesizing module 'lpgbtfpga_descrambler' (42#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_descrambler.vhd:45] INFO: [Synth 8-256] done synthesizing module 'lpgbtfpga_uplink_fixed' (43#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/lpgbtfpga_uplink_fixed.vhd:91] INFO: [Synth 8-638] synthesizing module 'bit_synchronizer__parameterized1' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/common/bit_synchronizer.vhd:75] Parameter INITIALIZE bound to: 5'b00000 INFO: [Synth 8-256] done synthesizing module 'bit_synchronizer__parameterized1' (43#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/common/bit_synchronizer.vhd:75] Parameter BUFGCE_DIVIDE bound to: 8 - type: integer Parameter CE_TYPE bound to: SYNC - type: string Parameter HARDSYNC_CLR bound to: FALSE - type: string Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_CLR_INVERTED bound to: 1'b0 Parameter IS_I_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: ULTRASCALE - type: string Parameter STARTUP_SYNC bound to: FALSE - type: string INFO: [Synth 8-6157] synthesizing module 'upLinkTxDataPath' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkTxDataPath.v:40] INFO: [Synth 8-6157] synthesizing module 'upLinkDataSelect' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkDataSelect.v:34] Parameter FEC5 bound to: 1'b0 Parameter FEC12 bound to: 1'b1 Parameter DR5G bound to: 1'b0 Parameter DR10G bound to: 1'b1 INFO: [Synth 8-6155] done synthesizing module 'upLinkDataSelect' (44#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkDataSelect.v:34] INFO: [Synth 8-6157] synthesizing module 'upLinkScrambler' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkScrambler.v:35] Parameter FEC5 bound to: 1'b0 Parameter FEC12 bound to: 1'b1 Parameter TxDataRate5G12 bound to: 1'b0 Parameter TxDataRate10G24 bound to: 1'b1 INFO: [Synth 8-6157] synthesizing module 'scrambler58bitOrder58' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler58bitOrder58.v:14] Parameter INIT_SEED bound to: 58'b0100010010101010111010101000010010001100011011101000010001 INFO: [Synth 8-6155] done synthesizing module 'scrambler58bitOrder58' (45#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler58bitOrder58.v:14] INFO: [Synth 8-6157] synthesizing module 'scrambler60bitOrder58' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler60bitOrder58.v:15] Parameter INIT_SEED bound to: 60'b000111111010101010110001001001001100101011011110000100010001 INFO: [Synth 8-6155] done synthesizing module 'scrambler60bitOrder58' (46#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler60bitOrder58.v:15] INFO: [Synth 8-6157] synthesizing module 'scrambler51bitOrder49' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler51bitOrder49.v:15] Parameter INIT_SEED bound to: 51'b111111100011000001101011011101010101100101000010100 INFO: [Synth 8-6155] done synthesizing module 'scrambler51bitOrder49' (47#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler51bitOrder49.v:15] INFO: [Synth 8-6157] synthesizing module 'scrambler53bitOrder49' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler53bitOrder49.v:15] Parameter INIT_SEED bound to: 53'b11111000101100011010010001010101010110001101000011010 INFO: [Synth 8-6155] done synthesizing module 'scrambler53bitOrder49' (48#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler53bitOrder49.v:15] INFO: [Synth 8-6155] done synthesizing module 'upLinkScrambler' (49#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkScrambler.v:35] INFO: [Synth 8-6157] synthesizing module 'upLinkFECEncoder' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkFECEncoder.v:34] INFO: [Synth 8-6157] synthesizing module 'rs_encoder_N31K29' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v:30] Parameter N bound to: 31 - type: integer Parameter K bound to: 29 - type: integer Parameter SYMB_BITWIDTH bound to: 5 - type: integer Parameter P bound to: 2 - type: integer Parameter INP_BW bound to: 145 - type: integer Parameter OUT_BW bound to: 155 - type: integer Parameter POL_BW bound to: 10 - type: integer Parameter STG_BW bound to: 15 - type: integer INFO: [Synth 8-6157] synthesizing module 'gf_add_5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_add_5.v:1] INFO: [Synth 8-6155] done synthesizing module 'gf_add_5' (50#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_add_5.v:1] INFO: [Synth 8-6157] synthesizing module 'gf_multBy2_5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy2_5.v:1] INFO: [Synth 8-6155] done synthesizing module 'gf_multBy2_5' (51#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy2_5.v:1] INFO: [Synth 8-6157] synthesizing module 'gf_multBy3_5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy3_5.v:1] INFO: [Synth 8-6155] done synthesizing module 'gf_multBy3_5' (52#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy3_5.v:1] INFO: [Synth 8-6155] done synthesizing module 'rs_encoder_N31K29' (53#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v:30] INFO: [Synth 8-6157] synthesizing module 'rs_encoder_N15K13' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v:30] Parameter N bound to: 15 - type: integer Parameter K bound to: 13 - type: integer Parameter SYMB_BITWIDTH bound to: 4 - type: integer Parameter P bound to: 2 - type: integer Parameter INP_BW bound to: 52 - type: integer Parameter OUT_BW bound to: 60 - type: integer Parameter POL_BW bound to: 8 - type: integer Parameter STG_BW bound to: 12 - type: integer INFO: [Synth 8-6157] synthesizing module 'gf_add_4' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_add_4.v:1] INFO: [Synth 8-6155] done synthesizing module 'gf_add_4' (54#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_add_4.v:1] INFO: [Synth 8-6157] synthesizing module 'gf_multBy2_4' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy2_4.v:1] INFO: [Synth 8-6155] done synthesizing module 'gf_multBy2_4' (55#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy2_4.v:1] INFO: [Synth 8-6157] synthesizing module 'gf_multBy3_4' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy3_4.v:1] INFO: [Synth 8-6155] done synthesizing module 'gf_multBy3_4' (56#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy3_4.v:1] INFO: [Synth 8-6155] done synthesizing module 'rs_encoder_N15K13' (57#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v:30] INFO: [Synth 8-6155] done synthesizing module 'upLinkFECEncoder' (58#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkFECEncoder.v:34] INFO: [Synth 8-6157] synthesizing module 'upLinkInterleaver' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkInterleaver.v:28] Parameter FEC5 bound to: 1'b0 Parameter FEC12 bound to: 1'b1 Parameter TxDataRate5G12 bound to: 1'b0 Parameter TxDataRate10G24 bound to: 1'b1 Parameter HEADER bound to: 2'b10 INFO: [Synth 8-6155] done synthesizing module 'upLinkInterleaver' (59#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkInterleaver.v:28] INFO: [Synth 8-6155] done synthesizing module 'upLinkTxDataPath' (60#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkTxDataPath.v:40] Parameter WORD_WIDTH bound to: 32 - type: integer Parameter DATA_RATE bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'upLinkTxGearBox' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkTxGearBox.v:29] Parameter WORD_WIDTH bound to: 32 - type: integer Parameter DATA_RATE bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'upLinkTxGearBox' (61#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkTxGearBox.v:29] INFO: [Synth 8-256] done synthesizing module 'TCDS2_if' (62#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/TTC_if/TCDS2_if.vhd:71] Parameter BLK_No bound to: 0 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 0 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer Parameter INITIAL_DELAY bound to: 50000000 - type: integer INFO: [Synth 8-638] synthesizing module 'xlx_ku_gbt_ngFEC_design' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd:165] Parameter BLK_No bound to: 0 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 0 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer Parameter INITIAL_DELAY bound to: 50000000 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_bank_reset' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_reset.vhd:114] Parameter INITIAL_DELAY bound to: 50000000 - type: integer INFO: [Synth 8-256] done synthesizing module 'gbt_bank_reset' (63#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_reset.vhd:114] INFO: [Synth 8-638] synthesizing module 'gbt_bankx12' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_bankx12.vhd:104] Parameter BLK_No bound to: 0 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 0 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'mgtX12' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/mgtX12.vhd:65] Parameter BLK_No bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'mgt_ip_example_init' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip_example_init.v:59] Parameter P_FREERUN_FREQUENCY bound to: 50.000000 - type: double Parameter P_TX_TIMER_DURATION_US bound to: 30000.000000 - type: double Parameter P_RX_TIMER_DURATION_US bound to: 130000.000000 - type: double Parameter ST_START bound to: 2'b00 Parameter ST_TX_WAIT bound to: 2'b01 Parameter ST_RX_WAIT bound to: 2'b10 Parameter ST_MONITOR bound to: 2'b11 INFO: [Synth 8-6157] synthesizing module 'mgt_ip_example_reset_synchronizer' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip_example_reset_sync.v:58] Parameter FREQUENCY bound to: 512 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mgt_ip_example_reset_synchronizer' (64#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip_example_reset_sync.v:58] INFO: [Synth 8-6157] synthesizing module 'mgt_ip_example_bit_synchronizer' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip_example_bit_sync.v:58] Parameter INITIALIZE bound to: 5'b00000 Parameter FREQUENCY bound to: 512 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mgt_ip_example_bit_synchronizer' (65#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip_example_bit_sync.v:58] INFO: [Synth 8-6155] done synthesizing module 'mgt_ip_example_init' (66#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip_example_init.v:59] INFO: [Synth 8-638] synthesizing module 'mgt_HPTD' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/mgt_HPTD.vhd:79] INFO: [Synth 8-638] synthesizing module 'mgt_ip' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/synth_1/.Xil/Vivado-15344-baby/realtime/mgt_ip_stub.vhdl:60] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single__parameterized2' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single__parameterized2' (66#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] INFO: [Synth 8-638] synthesizing module 'tx_phase_aligner' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/tx_phase_aligner.vhd:168] Parameter g_DRP_NPORT_CTRL bound to: 1 - type: bool Parameter g_DRP_ADDR_TXPI_PPM_CFG bound to: 9'b010011010 Parameter g_SPEED_PD_FACTOR bound to: 7 - type: integer Parameter g_PI_COARSE_STEP bound to: 8 - type: integer Parameter g_PI_FINE_STEP bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'tx_phase_aligner_fsm' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/tx_phase_aligner_fsm.vhd:116] Parameter g_SPEED_PD_FACTOR bound to: 7 - type: integer Parameter g_PI_COARSE_STEP bound to: 8 - type: integer Parameter g_PI_FINE_STEP bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'tx_phase_aligner_fsm' (67#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/tx_phase_aligner_fsm.vhd:116] Parameter g_DRP_NPORT_CTRL bound to: 1 - type: bool Parameter g_DRP_ADDR_TXPI_PPM_CFG bound to: 9'b010011010 INFO: [Synth 8-638] synthesizing module 'tx_pi_ctrl' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/tx_pi_ctrl.vhd:115] Parameter g_DRP_NPORT_CTRL bound to: 1 - type: bool Parameter g_DRP_ADDR_TXPI_PPM_CFG bound to: 9'b010011010 INFO: [Synth 8-256] done synthesizing module 'tx_pi_ctrl' (68#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/tx_pi_ctrl.vhd:115] INFO: [Synth 8-638] synthesizing module 'fifo_fill_level_acc' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/fifo_fill_level_acc.vhd:88] INFO: [Synth 8-256] done synthesizing module 'fifo_fill_level_acc' (69#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/fifo_fill_level_acc.vhd:88] INFO: [Synth 8-256] done synthesizing module 'tx_phase_aligner' (70#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/tx_phase_aligner.vhd:168] INFO: [Synth 8-256] done synthesizing module 'mgt_HPTD' (71#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/mgt_HPTD.vhd:79] INFO: [Synth 8-638] synthesizing module 'mgt_bitslipctrl' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_bitslipctrl.vhd:58] INFO: [Synth 8-256] done synthesizing module 'mgt_bitslipctrl' (72#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_bitslipctrl.vhd:58] INFO: [Synth 8-638] synthesizing module 'mgt_framealigner_pattsearch' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_framealigner_pattsearch.vhd:59] INFO: [Synth 8-256] done synthesizing module 'mgt_framealigner_pattsearch' (73#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_framealigner_pattsearch.vhd:59] INFO: [Synth 8-256] done synthesizing module 'mgtX12' (74#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/mgtX12.vhd:65] INFO: [Synth 8-638] synthesizing module 'gbt_tx' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx.vhd:41] Parameter TX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_tx_scrambler' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler.vhd:78] Parameter TX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_tx_scrambler_21bit' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler_21bit.vhd:58] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_scrambler_21bit' (75#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler_21bit.vhd:58] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_scrambler' (76#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler.vhd:78] INFO: [Synth 8-638] synthesizing module 'gbt_tx_encoder' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder.vhd:69] Parameter TX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_tx_encoder_gbtframe_rsencode' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_rsencode.vhd:31] INFO: [Synth 8-638] synthesizing module 'gbt_tx_encoder_gbtframe_polydiv' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_polydiv.vhd:33] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_encoder_gbtframe_polydiv' (77#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_polydiv.vhd:33] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_encoder_gbtframe_rsencode' (78#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_rsencode.vhd:31] INFO: [Synth 8-638] synthesizing module 'gbt_tx_encoder_gbtframe_intlver' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_intlver.vhd:28] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_encoder_gbtframe_intlver' (79#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_intlver.vhd:28] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_encoder' (80#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder.vhd:69] INFO: [Synth 8-256] done synthesizing module 'gbt_tx' (81#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx.vhd:41] INFO: [Synth 8-638] synthesizing module 'gbt_tx_gearbox' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_tx_gearbox.vhd:65] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_gearbox' (82#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_tx_gearbox.vhd:65] INFO: [Synth 8-638] synthesizing module 'gbt_rx_gearbox' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_rx_gearbox.vhd:51] Parameter RX_OPTIMIZATION bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'gbt_rx_gearbox' (83#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_rx_gearbox.vhd:51] INFO: [Synth 8-638] synthesizing module 'gbt_rx' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx.vhd:54] Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd:57] Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_deintlver' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_deintlver.vhd:35] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_deintlver' (84#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_deintlver.vhd:35] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_rsdec' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rsdec.vhd:46] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_syndrom' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_syndrom.vhd:42] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_syndrom' (85#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_syndrom.vhd:42] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_lmbddet' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_lmbddet.vhd:42] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_lmbddet' (86#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_lmbddet.vhd:42] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_errlcpoly' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_errlcpoly.vhd:44] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd:130] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd:130] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd:130] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd:130] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_errlcpoly' (87#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_errlcpoly.vhd:44] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_chnsrch' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_chnsrch.vhd:44] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_elpeval' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_elpeval.vhd:41] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_elpeval' (88#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_elpeval.vhd:41] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd:130] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd:130] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_chnsrch' (89#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_chnsrch.vhd:44] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_rs2errcor' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rs2errcor.vhd:45] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd:130] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd:130] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd:155] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd:155] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_rs2errcor' (90#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rs2errcor.vhd:45] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_rsdec' (91#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rsdec.vhd:46] WARNING: [Synth 8-614] signal 'RX_RESET_I' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd:124] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder' (92#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd:57] INFO: [Synth 8-638] synthesizing module 'gbt_rx_descrambler' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler.vhd:57] Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_rx_descrambler_21bit' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler_21bit.vhd:56] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_descrambler_21bit' (93#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler_21bit.vhd:56] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_descrambler' (94#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler.vhd:57] INFO: [Synth 8-256] done synthesizing module 'gbt_rx' (95#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx.vhd:54] INFO: [Synth 8-256] done synthesizing module 'gbt_bankx12' (96#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_bankx12.vhd:104] INFO: [Synth 8-256] done synthesizing module 'xlx_ku_gbt_ngFEC_design' (97#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd:165] Parameter BLK_No bound to: 1 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 0 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer Parameter INITIAL_DELAY bound to: 50000000 - type: integer INFO: [Synth 8-638] synthesizing module 'xlx_ku_gbt_ngFEC_design__parameterized1' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd:165] Parameter BLK_No bound to: 1 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 0 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer Parameter INITIAL_DELAY bound to: 50000000 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_bankx12__parameterized0' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_bankx12.vhd:104] Parameter BLK_No bound to: 1 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 0 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'mgtX12__parameterized0' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/mgtX12.vhd:65] Parameter BLK_No bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'mgtX12__parameterized0' (97#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/mgtX12.vhd:65] INFO: [Synth 8-256] done synthesizing module 'gbt_bankx12__parameterized0' (97#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_bankx12.vhd:104] INFO: [Synth 8-256] done synthesizing module 'xlx_ku_gbt_ngFEC_design__parameterized1' (97#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd:165] Parameter BLK_No bound to: 2 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 0 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer Parameter INITIAL_DELAY bound to: 50000000 - type: integer INFO: [Synth 8-638] synthesizing module 'xlx_ku_gbt_ngFEC_design__parameterized3' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd:165] Parameter BLK_No bound to: 2 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 0 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer Parameter INITIAL_DELAY bound to: 50000000 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_bankx12__parameterized1' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_bankx12.vhd:104] Parameter BLK_No bound to: 2 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 0 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'mgtX12__parameterized1' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/mgtX12.vhd:65] Parameter BLK_No bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'mgtX12__parameterized1' (97#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/mgtX12.vhd:65] INFO: [Synth 8-256] done synthesizing module 'gbt_bankx12__parameterized1' (97#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_bankx12.vhd:104] INFO: [Synth 8-256] done synthesizing module 'xlx_ku_gbt_ngFEC_design__parameterized3' (97#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd:165] Parameter BLK_No bound to: 3 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 0 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer Parameter INITIAL_DELAY bound to: 50000000 - type: integer INFO: [Synth 8-638] synthesizing module 'xlx_ku_gbt_ngFEC_design__parameterized5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd:165] Parameter BLK_No bound to: 3 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 0 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer Parameter INITIAL_DELAY bound to: 50000000 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_bankx12__parameterized2' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_bankx12.vhd:104] Parameter BLK_No bound to: 3 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 0 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'mgtX12__parameterized2' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/mgtX12.vhd:65] Parameter BLK_No bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'mgtX12__parameterized2' (97#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/mgtX12.vhd:65] INFO: [Synth 8-256] done synthesizing module 'gbt_bankx12__parameterized2' (97#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/gbt_bankx12.vhd:104] INFO: [Synth 8-256] done synthesizing module 'xlx_ku_gbt_ngFEC_design__parameterized5' (97#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd:165] INFO: [Synth 8-638] synthesizing module 'prbs' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/GBT_tools/prbs.vhd:43] Parameter seed bound to: 20'b00101010001000000001 Parameter inverter bound to: 0 - type: bool Parameter hbhehf bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'prbs' (98#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/GBT_tools/prbs.vhd:43] INFO: [Synth 8-638] synthesizing module 'ngFEC_module' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/ngFEC_module.vhd:58] INFO: [Synth 8-638] synthesizing module 'Module_RAM' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/Module_RAM.vhd:47] Parameter MEMORY_SIZE bound to: 65536 - type: integer Parameter MEMORY_PRIMITIVE bound to: block - type: string Parameter CLOCKING_MODE bound to: common_clock - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: disable_sleep - type: string Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 11 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 1 - type: integer Parameter WRITE_MODE_A bound to: no_change - type: string Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 11 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: no_change - type: string Parameter RST_MODE_B bound to: SYNC - type: string INFO: [Synth 8-6157] synthesizing module 'xpm_memory_tdpram__parameterized2' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8871] Parameter MEMORY_SIZE bound to: 65536 - type: integer Parameter MEMORY_PRIMITIVE bound to: block - type: string Parameter CLOCKING_MODE bound to: common_clock - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: disable_sleep - type: string Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 11 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 1 - type: integer Parameter WRITE_MODE_A bound to: no_change - type: string Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 11 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: no_change - type: string Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter P_CLOCKING_MODE bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 0 - type: integer Parameter P_WRITE_MODE_A bound to: 2 - type: integer Parameter P_WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_OPTIMIZATION bound to: 1 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized0' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 2 - type: integer Parameter MEMORY_SIZE bound to: 65536 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 11 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 1 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 11 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 2048 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 11 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 11 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 11 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 11 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: yes - type: string Parameter rsta_loop_iter bound to: 32 - type: integer Parameter rstb_loop_iter bound to: 32 - type: integer Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:490] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized0' (98#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_tdpram__parameterized2' (98#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8871] Parameter MEMORY_SIZE bound to: 16384 - type: integer Parameter MEMORY_PRIMITIVE bound to: block - type: string Parameter CLOCKING_MODE bound to: common_clock - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: disable_sleep - type: string Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: no_change - type: string Parameter RST_MODE_B bound to: SYNC - type: string INFO: [Synth 8-6157] synthesizing module 'xpm_memory_sdpram' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8404] Parameter MEMORY_SIZE bound to: 16384 - type: integer Parameter MEMORY_PRIMITIVE bound to: block - type: string Parameter CLOCKING_MODE bound to: common_clock - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: disable_sleep - type: string Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: no_change - type: string Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter P_CLOCKING_MODE bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 0 - type: integer Parameter P_WRITE_MODE_B bound to: 2 - type: integer Parameter P_MEMORY_OPTIMIZATION bound to: 1 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized1' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 16384 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter USE_MEM_INIT bound to: 1 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter rsta_loop_iter bound to: 32 - type: integer Parameter rstb_loop_iter bound to: 32 - type: integer Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:490] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized1' (98#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_sdpram' (99#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8404] INFO: [Synth 8-256] done synthesizing module 'Module_RAM' (100#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/Module_RAM.vhd:47] Parameter partition bound to: 5'b00000 INFO: [Synth 8-638] synthesizing module 'buffer_server_com' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00000 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00001 INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized1' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00001 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized1' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00010 INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized3' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00010 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized3' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00011 INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized5' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00011 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized5' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00100 INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized7' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00100 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized7' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00101 INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized9' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00101 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized9' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00110 INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized11' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00110 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized11' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00111 INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized13' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b00111 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized13' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b01000 INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized15' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b01000 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized15' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b01001 INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized17' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b01001 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized17' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b01010 INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized19' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b01010 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized19' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b01011 INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized21' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b01011 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized21' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b01111 INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized23' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b01111 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized23' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b11111 INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized25' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] Parameter partition bound to: 5'b11111 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized25' (101#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd:46] INFO: [Synth 8-638] synthesizing module 'buffer_ngccm_com' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_ngccm_comNew.vhd:48] INFO: [Synth 8-256] done synthesizing module 'buffer_ngccm_com' (102#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_ngccm_comNew.vhd:48] INFO: [Synth 8-638] synthesizing module 'buffer_ngccm_jtag_com' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_ngccm_jtag_comNew.vhd:49] INFO: [Synth 8-256] done synthesizing module 'buffer_ngccm_jtag_com' (103#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/buffer_ngccm_jtag_comNew.vhd:49] INFO: [Synth 8-256] done synthesizing module 'ngFEC_module' (104#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngFEC_module/ngFEC_module.vhd:58] Parameter orbit bound to: 3564 - type: integer INFO: [Synth 8-638] synthesizing module 'delay_counter' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/delay_counter.vhd:41] Parameter orbit bound to: 3564 - type: integer INFO: [Synth 8-256] done synthesizing module 'delay_counter' (105#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/delay_counter.vhd:41] INFO: [Synth 8-638] synthesizing module 'ngCCM' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/ngCCM.vhd:94] INFO: [Synth 8-638] synthesizing module 'SyncRst' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/SyncRst.vhd:34] INFO: [Synth 8-256] done synthesizing module 'SyncRst' (106#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/SyncRst.vhd:34] INFO: [Synth 8-638] synthesizing module 'gbt_rx_checker' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/GBT_tools/gbt_rx_checker.vhd:44] Parameter seed_length bound to: 20 - type: integer Parameter nobReg bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'gbt_rx_checker' (107#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/GBT_tools/gbt_rx_checker.vhd:44] Parameter DataBtoA_SZ bound to: 1 - type: integer Parameter DataAtoB_SZ bound to: 84 - type: integer Parameter WAIT_STATES_A bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'CrossClock_RX' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v:20] Parameter DataBtoA_SZ bound to: 1 - type: integer Parameter DataAtoB_SZ bound to: 84 - type: integer Parameter WAIT_STATES_A bound to: 0 - type: integer Parameter SHIFTA_MSB bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module 'CrossClock_RX' (108#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v:20] Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'IPbus_local' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/IPbus_local.vhd:58] Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'IPbus_local' (109#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/IPbus_local.vhd:58] Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'LocalI2CBridge' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/LocalI2CBridge.vhd:79] Parameter ARST_LVL bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'i2c_master_usr' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/i2c_master_top.vhd:113] Parameter ARST_LVL bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'i2c_master_byte_ctrl' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/i2c_master_byte_ctrl.vhd:114] INFO: [Synth 8-638] synthesizing module 'i2c_master_bit_ctrl' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/i2c_master_bit_ctrl.vhd:179] Parameter SIZE bound to: 8 - type: integer Parameter DOUT_RST bound to: 1'b1 INFO: [Synth 8-6157] synthesizing module 'glitch_filter' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/glitch_filter.v:57] Parameter SIZE bound to: 8 - type: integer Parameter DOUT_RST bound to: 1'b1 Parameter BUFSIZE bound to: 7 - type: integer INFO: [Synth 8-6155] done synthesizing module 'glitch_filter' (110#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/glitch_filter.v:57] Parameter SIZE bound to: 8 - type: integer Parameter DOUT_RST bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'i2c_master_bit_ctrl' (111#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/i2c_master_bit_ctrl.vhd:179] INFO: [Synth 8-256] done synthesizing module 'i2c_master_byte_ctrl' (112#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/i2c_master_byte_ctrl.vhd:114] INFO: [Synth 8-256] done synthesizing module 'i2c_master_usr' (113#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/i2c_master_top.vhd:113] INFO: [Synth 8-256] done synthesizing module 'LocalI2CBridge' (114#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/LocalI2CBridge.vhd:79] INFO: [Synth 8-638] synthesizing module 'LocalJTAGBridge' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/LocalJTAGBridge.vhd:94] Parameter gADDR_BITS bound to: 10 - type: integer Parameter gDATA_BITS bound to: 32 - type: integer INFO: [Synth 8-638] synthesizing module 'JTAGMaster' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/jtagMaster.vhd:92] Parameter gADDR_BITS bound to: 10 - type: integer Parameter gDATA_BITS bound to: 32 - type: integer Parameter gADDR_BITS bound to: 10 - type: integer Parameter gDATA_BITS bound to: 32 - type: integer INFO: [Synth 8-638] synthesizing module 'RAM' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/jtagBram.vhd:66] Parameter gADDR_BITS bound to: 10 - type: integer Parameter gDATA_BITS bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAM' (115#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/jtagBram.vhd:66] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'JTAGMaster' (116#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/jtagMaster.vhd:92] INFO: [Synth 8-256] done synthesizing module 'LocalJTAGBridge' (117#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/LocalJTAGBridge.vhd:94] WARNING: [Synth 8-614] signal 'sel_sec_jtag' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/ngCCM.vhd:1086] WARNING: [Synth 8-614] signal 'sel_sec_jtag' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/ngCCM.vhd:1107] WARNING: [Synth 8-614] signal 'sel_sec_jtag' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/ngCCM.vhd:1127] INFO: [Synth 8-256] done synthesizing module 'ngCCM' (118#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/ngCCM.vhd:94] Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer INFO: [Synth 8-638] synthesizing module 'I2C_if' [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/I2C_if.vhd:54] Parameter WAIT_STATES bound to: 10 - type: integer Parameter partition bound to: 5'b00000 Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter partition bound to: 5'b00001 Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter partition bound to: 5'b00010 Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter partition bound to: 5'b00011 Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter partition bound to: 5'b00100 Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter partition bound to: 5'b00101 Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter partition bound to: 5'b00110 Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter partition bound to: 5'b00111 Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter partition bound to: 5'b01000 Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-256] done synthesizing module 'I2C_if' (119#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/I2C_if.vhd:54] INFO: [Synth 8-256] done synthesizing module 'ngFEC_top' (120#1) [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC_top.vhd:77] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1965.434 ; gain = 750.270 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 1982.672 ; gain = 767.508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 1982.672 ; gain = 767.508 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 4608.340 ; gain = 130.742 INFO: [Netlist 29-17] Analyzing 1031 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 17 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B/axi_chip2chip_64B66B_in_context.xdc] for cell 'i_axi_slave/i_axi_chip2chip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B/axi_chip2chip_64B66B_in_context.xdc] for cell 'i_axi_slave/i_axi_chip2chip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/ttc_mgt/ttc_mgt_in_context.xdc] for cell 'i_tcds2_if/i_mgt_wrapper/i_mgt' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/ttc_mgt/ttc_mgt_in_context.xdc] for cell 'i_tcds2_if/i_mgt_wrapper/i_mgt' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0/aurora_64b66b_0_in_context.xdc] for cell 'i_axi_slave/i_aurora' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0/aurora_64b66b_0_in_context.xdc] for cell 'i_axi_slave/i_aurora' Parsing XDC File [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc] INFO: [Timing 38-2] Deriving generated clocks [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:126] get_clocks: Time (s): cpu = 00:00:54 ; elapsed = 00:00:34 . Memory (MB): peak = 7908.629 ; gain = 269.914 WARNING: [Vivado 12-508] No pins matched 'stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]'. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:136] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:137] WARNING: [Vivado 12-508] No pins matched 'stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]'. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:138] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:139] WARNING: [Vivado 12-508] No pins matched 'stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]'. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:140] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:141] WARNING: [Vivado 12-508] No pins matched 'stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]'. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:142] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:143] WARNING: [Vivado 12-508] No pins matched 'stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/ADDRARDADDR[*]'. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:144] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:145] WARNING: [Vivado 12-508] No pins matched 'stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/CLKARDCLK'. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:146] WARNING: [Vivado 12-508] No pins matched 'stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]'. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:146] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:147] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:149] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:151] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:153] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:155] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:157] Finished Parsing XDC File [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc] WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/ngFEC_top_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ngFEC_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ngFEC_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. write_xdc: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 7908.629 ; gain = 0.000 INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ngFEC_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ngFEC_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] INFO: [Common 17-14] Message 'Vivado 12-180' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] INFO: [Common 17-14] Message 'Common 17-55' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ngFEC_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ngFEC_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ngFEC_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ngFEC_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. write_xdc: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 7908.629 ; gain = 0.000 Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.573 . Memory (MB): peak = 7930.402 ; gain = 4.703 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1030 instances were transformed. BUFG => BUFGCE: 8 instances DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 1003 instances IOBUF => IOBUF (IBUFCTRL, INBUF, OBUFT): 18 instances MMCME3_BASE => MMCME3_ADV: 1 instance write_xdc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 7969.586 ; gain = 0.000 Constraint Validation Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 7969.586 ; gain = 39.141 WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip' at clock pin 'drpclk_in[0]' is different from the actual clock period '8.317', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'i_axi_slave/i_axi_chip2chip' at clock pin 'm_aclk' is different from the actual clock period '8.000', this can lead to different synthesis results. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:08:18 ; elapsed = 00:07:29 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xcku115-flva2104-1-c INFO: [Synth 8-6742] Reading net delay rules and data Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxn[40]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxp[40]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxp[40]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txn[40]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txn[40]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txp[40]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txp[40]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxn[41]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxn[41]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxp[41]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxp[41]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txn[41]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txn[41]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txp[41]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txp[41]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxn[42]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxn[42]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxp[42]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxp[42]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txn[42]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txn[42]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txp[42]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txp[42]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxn[43]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxn[43]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxp[43]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxp[43]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txn[43]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txn[43]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txp[43]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txp[43]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxn[44]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxn[44]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxp[44]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxp[44]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txn[44]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txn[44]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txp[44]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txp[44]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxn[45]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxn[45]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxp[45]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxp[45]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txn[45]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txn[45]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txp[45]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txp[45]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxn[46]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxn[46]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxp[46]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxp[46]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txn[46]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txn[46]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txp[46]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txp[46]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxn[47]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxn[47]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for GBT_rxp[47]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_rxp[47]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txn[47]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txn[47]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for GBT_txp[47]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for GBT_txp[47]. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for TTC_rxn. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/ttc_mgt/ttc_mgt_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for TTC_rxn. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/ttc_mgt/ttc_mgt_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for TTC_rxp. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/ttc_mgt/ttc_mgt_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for TTC_rxp. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/ttc_mgt/ttc_mgt_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for TTC_txn. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/ttc_mgt/ttc_mgt_in_context.xdc, line 11). Applied set_property CLOCK_BUFFER_TYPE = NONE for TTC_txn. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/ttc_mgt/ttc_mgt_in_context.xdc, line 12). Applied set_property IO_BUFFER_TYPE = NONE for TTC_txp. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/ttc_mgt/ttc_mgt_in_context.xdc, line 13). Applied set_property CLOCK_BUFFER_TYPE = NONE for TTC_txp. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/ttc_mgt/ttc_mgt_in_context.xdc, line 14). Applied set_property IO_BUFFER_TYPE = NONE for c2c_rxn. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0/aurora_64b66b_0_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for c2c_rxn. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0/aurora_64b66b_0_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for c2c_rxp. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0/aurora_64b66b_0_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for c2c_rxp. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0/aurora_64b66b_0_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for c2c_txn. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0/aurora_64b66b_0_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for c2c_txn. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0/aurora_64b66b_0_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for c2c_txp. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0/aurora_64b66b_0_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for c2c_txp. (constraint file d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0/aurora_64b66b_0_in_context.xdc, line 10). Applied set_property KEEP_HIERARCHY = SOFT for i_axi_slave/i_axi_chip2chip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[0].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[1].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[2].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[3].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[4].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[5].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[6].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[7].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[8].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[9].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[10].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[11].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[0].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[1].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[2].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[3].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[4].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[5].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[6].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[7].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[8].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[9].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[10].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[11].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[0].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[1].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[2].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[3].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[4].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[5].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[6].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[7].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[8].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[9].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[10].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[11].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[0].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[1].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[2].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[3].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[4].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[5].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[6].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[7].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[8].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[9].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[10].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[11].i_mgt_ip_rx_buf /i_mgt_ip. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_tcds2_if/i_mgt_wrapper/i_mgt. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_axi_slave/i_aurora. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[0].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[1].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[2].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[3].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[4].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[5].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[6].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[7].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[8].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[9].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[10].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[11].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[12].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[13].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[14].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[15].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[16].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[17].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[18].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[19].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[20].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[21].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[22].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[23].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[24].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[25].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[26].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[27].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[28].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[29].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[30].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[31].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[32].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[33].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[34].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[35].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[36].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[37].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[38].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[39].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[40].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[41].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[42].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[43].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[44].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[45].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[46].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[47].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[48].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[49].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[50].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[51].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[52].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[53].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[54].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[55].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[56].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[57].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[58].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[59].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[60].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[61].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[62].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[63].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[64].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[65].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[66].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[67].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[68].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[69].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[70].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[71].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[72].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[73].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[74].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[75].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[76].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[77].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[78].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[79].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[80].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[81].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[82].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[83].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[84].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[85].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[86].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[87].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[88].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[89].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[90].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[91].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[92].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[93].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[94].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[95].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[96].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[97].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[98].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[99].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[100].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[101].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[102].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[103].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[104].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[105].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[106].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[107].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[108].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[109].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[110].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[111].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[112].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[113].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[114].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[115].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[116].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[117].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[118].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[119].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[120].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[121].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[122].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[123].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[124].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[125].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[126].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[127].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[0].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[1].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[2].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[3].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[4].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[5].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[6].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[7].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[8].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[9].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[10].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[11].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[12].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[13].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[14].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[15].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[16].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[17].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[18].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[19].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[20].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[21].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[22].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[23].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[24].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[25].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[26].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[27].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[28].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[29].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[30].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[31].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[32].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[33].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[34].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[35].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[36].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[37].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[38].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[39].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[40].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[41].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[42].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[43].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[44].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[45].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[46].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[47].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[48].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[49].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[50].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[51].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[52].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[53].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[54].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[55].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[56].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[57].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[58].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[59].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[60].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[61].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[62].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[63].i_DSP_counterX4 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[0].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[0].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[0].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[0].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[1].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[1].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[1].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[1].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[2].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[2].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[2].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[2].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[3].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[3].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[3].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[3].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[4].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[4].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[4].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[4].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[5].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[5].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[5].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[5].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[6].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[6].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[6].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[6].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[7].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[7].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[7].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[7].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[8].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[8].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[8].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[8].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[9].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[9].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[9].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[9].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[10].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[10].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[10].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[10].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[11].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[11].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[11].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[11].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[12].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[12].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[12].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[12].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[13].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[13].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[13].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[13].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[14].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[14].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[14].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[14].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[15].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[15].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[15].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[15].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[16].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[16].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[16].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[16].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[17].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[17].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[17].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[17].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[18].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[18].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[18].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[18].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[19].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[19].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[19].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[19].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[20].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[20].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[20].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[20].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[21].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[21].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[21].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[21].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[22].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[22].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[22].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[22].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[23].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[23].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[23].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[23].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[24].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[24].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[24].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[24].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[25].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[25].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[25].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[25].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[26].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[26].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[26].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[26].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[27].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[27].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[27].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[27].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[28].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[28].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[28].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[28].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[29].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[29].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[29].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[29].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[30].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[30].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[30].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[30].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[31].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[31].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[31].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[31].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[32].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[32].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[32].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[32].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[33].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[33].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[33].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[33].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[34].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[34].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[34].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[34].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[35].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[35].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[35].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[35].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[36].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[36].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[36].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[36].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[37].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[37].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[37].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[37].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[38].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[38].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[38].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[38].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[39].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[39].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[39].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[39].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[40].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[40].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[40].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[40].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[41].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[41].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[41].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[41].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[42].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[42].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[42].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[42].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[43].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[43].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[43].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[43].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[44].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[44].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[44].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[44].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[45].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[45].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[45].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[45].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[46].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[46].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[46].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[46].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[47].i_rate_ngccm_status0 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[47].i_rate_ngccm_status1 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[47].i_rate_ngccm_status2 /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[47].i_rate_test_comm /\g_sync[0].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[0].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[1].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[2].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[3].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[4].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[5].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[6].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[7].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[8].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[9].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[10].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[11].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[12].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[13].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[14].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[15].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[16].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[17].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[18].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[19].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[20].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[21].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[22].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[23].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[24].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[25].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[26].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[27].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[28].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[29].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[30].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[31].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[32].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[33].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[34].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[35].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[36].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[37].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[38].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[39].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[40].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[41].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[42].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[43].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[44].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[45].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[46].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[47].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[48].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[49].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[50].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[51].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[52].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[53].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[54].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[55].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[56].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[57].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[58].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[59].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[60].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[61].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[62].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[63].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[64].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[65].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[66].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[67].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[68].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[69].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[70].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[71].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[72].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[73].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[74].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[75].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[76].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[77].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[78].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[79].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[80].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[81].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[82].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[83].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[84].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[85].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[86].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[87].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[88].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[89].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[90].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[91].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[92].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[93].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[94].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[95].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[96].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[97].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[98].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[99].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[100].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[101].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[102].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[103].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[104].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[105].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[106].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[107].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[108].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[109].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[110].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[111].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[112].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[113].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[114].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[115].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[116].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[117].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[118].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[119].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[120].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[121].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[122].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[123].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[124].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[125].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[126].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[127].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[0].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[1].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[2].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[3].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[4].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[5].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[6].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[7].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[8].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[9].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[10].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[11].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[12].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[13].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[14].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[15].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[16].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[17].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[18].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[19].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[20].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[21].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[22].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[23].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[24].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[25].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[26].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[27].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[28].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[29].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[30].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[31].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[32].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[33].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[34].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[35].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[36].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[37].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[38].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[39].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[40].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[41].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[42].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[43].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[44].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[45].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[46].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[47].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[48].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[49].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[50].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[51].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[52].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[53].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[54].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[55].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[56].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[57].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[58].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[59].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[60].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[61].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[62].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[63].i_DSP_counterX4 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[0].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[0].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[0].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[0].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[1].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[1].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[1].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[1].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[2].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[2].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[2].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[2].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[3].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[3].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[3].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[3].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[4].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[4].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[4].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[4].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[5].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[5].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[5].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[5].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[6].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[6].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[6].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[6].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[7].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[7].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[7].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[7].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[8].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[8].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[8].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[8].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[9].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[9].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[9].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[9].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[10].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[10].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[10].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[10].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[11].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[11].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[11].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[11].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[12].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[12].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[12].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[12].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[13].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[13].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[13].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[13].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[14].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[14].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[14].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[14].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[15].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[15].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[15].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[15].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[16].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[16].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[16].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[16].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[17].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[17].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[17].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[17].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[18].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[18].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[18].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[18].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[19].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[19].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[19].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[19].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[20].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[20].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[20].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[20].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[21].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[21].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[21].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[21].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[22].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[22].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[22].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[22].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[23].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[23].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[23].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[23].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[24].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[24].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[24].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[24].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[25].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[25].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[25].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[25].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[26].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[26].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[26].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[26].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[27].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[27].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[27].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[27].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[28].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[28].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[28].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[28].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[29].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[29].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[29].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[29].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[30].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[30].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[30].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[30].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[31].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[31].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[31].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[31].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[32].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[32].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[32].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[32].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[33].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[33].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[33].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[33].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[34].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[34].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[34].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[34].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[35].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[35].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[35].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[35].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[36].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[36].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[36].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[36].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[37].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[37].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[37].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[37].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[38].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[38].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[38].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[38].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[39].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[39].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[39].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[39].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[40].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[40].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[40].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[40].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[41].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[41].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[41].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[41].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[42].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[42].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[42].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[42].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[43].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[43].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[43].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[43].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[44].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[44].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[44].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[44].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[45].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[45].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[45].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[45].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[46].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[46].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[46].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[46].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[47].i_rate_ngccm_status0 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[47].i_rate_ngccm_status1 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[47].i_rate_ngccm_status2 /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[47].i_rate_test_comm /\g_sync[1].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[0].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[1].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[2].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[3].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[4].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[5].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[6].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[7].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[8].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[9].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[10].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[11].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[12].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[13].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[14].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[15].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[16].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[17].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[18].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[19].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[20].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[21].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[22].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[23].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[24].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[25].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[26].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[27].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[28].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[29].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[30].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[31].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[32].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[33].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[34].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[35].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[36].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[37].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[38].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[39].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[40].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[41].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[42].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[43].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[44].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[45].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[46].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[47].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[48].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[49].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[50].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[51].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[52].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[53].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[54].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[55].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[56].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[57].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[58].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[59].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[60].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[61].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[62].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[63].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[64].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[65].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[66].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[67].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[68].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[69].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[70].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[71].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[72].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[73].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[74].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[75].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[76].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[77].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[78].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[79].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[80].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[81].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[82].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[83].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[84].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[85].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[86].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[87].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[88].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[89].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[90].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[91].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[92].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[93].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[94].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[95].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[96].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[97].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[98].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[99].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[100].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[101].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[102].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[103].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[104].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[105].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[106].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[107].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[108].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[109].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[110].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[111].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[112].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[113].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[114].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[115].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[116].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[117].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[118].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[119].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[120].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[121].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[122].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[123].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[124].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[125].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[126].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[127].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[0].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[1].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[2].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[3].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[4].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[5].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[6].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[7].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[8].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[9].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[10].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[11].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[12].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[13].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[14].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[15].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[16].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[17].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[18].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[19].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[20].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[21].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[22].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[23].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[24].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[25].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[26].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[27].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[28].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[29].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[30].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[31].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[32].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[33].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[34].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[35].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[36].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[37].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[38].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[39].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[40].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[41].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[42].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[43].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[44].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[45].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[46].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[47].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[48].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[49].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[50].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[51].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[52].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[53].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[54].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[55].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[56].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[57].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[58].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[59].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[60].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[61].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[62].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[63].i_DSP_counterX4 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[0].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[0].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[0].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[1].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[1].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[1].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[2].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[2].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[2].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[3].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[3].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[3].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[4].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[4].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[4].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[5].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[5].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[5].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[6].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[6].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[6].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[7].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[7].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[7].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[8].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[8].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[8].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[9].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[9].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[9].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[10].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[10].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[10].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[11].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[11].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[11].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[12].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[12].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[12].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[13].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[13].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[13].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[14].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[14].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[14].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[15].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[15].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[15].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[16].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[16].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[16].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[17].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[17].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[17].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[18].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[18].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[18].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[19].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[19].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[19].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[20].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[20].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[20].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[21].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[21].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[21].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[22].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[22].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[22].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[23].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[23].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[23].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[24].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[24].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[24].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[25].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[25].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[25].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[26].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[26].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[26].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[27].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[27].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[27].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[28].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[28].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[28].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[29].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[29].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[29].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[30].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[30].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[30].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[31].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[31].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[31].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[32].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[32].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[32].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[33].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[33].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[33].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[34].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[34].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[34].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[35].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[35].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[35].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[36].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[36].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[36].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[37].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[37].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[37].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[38].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[38].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[38].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[39].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[39].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[39].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[40].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[40].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[40].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[41].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[41].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[41].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[42].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[42].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[42].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[43].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[43].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[43].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[44].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[44].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[44].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[45].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[45].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[45].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[46].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[46].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[46].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[47].i_rate_ngccm_status0 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[47].i_rate_ngccm_status1 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_clock_rate_din[47].i_rate_ngccm_status2 /\g_sync[2].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[0].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[1].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[2].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[3].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[4].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[5].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[6].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[7].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[8].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[9].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[10].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[11].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[12].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[13].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[14].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[15].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[16].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[17].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[18].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[19].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[20].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[21].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[22].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[23].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[24].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[25].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[26].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[27].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[28].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[29].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[30].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[31].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[32].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[33].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[34].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[35].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[36].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[37].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[38].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[39].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[40].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[41].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[42].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[43].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[44].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[45].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[46].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[47].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[48].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[49].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[50].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[51].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[52].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[53].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[54].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[55].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[56].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[57].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[58].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[59].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[60].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[61].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[62].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[63].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[64].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[65].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[66].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[67].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[68].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[69].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[70].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[71].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[72].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[73].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[74].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[75].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[76].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[77].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[78].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[79].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[80].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[81].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[82].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[83].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[84].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[85].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[86].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[87].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[88].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[89].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[90].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[91].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[92].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[93].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[94].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[95].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[96].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[97].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[98].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[99].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[100].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[101].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[102].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[103].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[104].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[105].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[106].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[107].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[108].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[109].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[110].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[111].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[112].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[113].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[114].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[115].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[116].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[117].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[118].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[119].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[120].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[121].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[122].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[123].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[124].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[125].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[126].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_cntr[127].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[0].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[1].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[2].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[3].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[4].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[5].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[6].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[7].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[8].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[9].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[10].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[11].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[12].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[13].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[14].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[15].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[16].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[17].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[18].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[19].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[20].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[21].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[22].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[23].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[24].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[25].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[26].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[27].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[28].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[29].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[30].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[31].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[32].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[33].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[34].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[35].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[36].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[37].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[38].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[39].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[40].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[41].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[42].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[43].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[44].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[45].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[46].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[47].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[48].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[49].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[50].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[51].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[52].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[53].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[54].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[55].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[56].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[57].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[58].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[59].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[60].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[61].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[62].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/\g_DSP_rate[63].i_DSP_counterX4 /\g_sync[3].g_cdc.xpm_cdc_single_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[12].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /IPbus_strobe_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[10].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[11].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[12].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[13].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[14].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[15].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[16].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[17].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[18].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[19].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[1].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[20].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[21].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[22].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[23].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[24].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[25].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[26].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[27].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[28].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[29].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[2].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[30].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[31].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[32].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[33].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[34].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[35].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[36].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[37].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[38].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[39].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[3].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[40].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[41].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[42].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[43].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[44].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[45].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[46].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[47].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[4].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[5].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[6].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[7].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[8].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_rx_frameclk_lock_cnt[9].rx_frameclk_lock_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[0].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[10].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[11].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[12].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[13].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[14].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[15].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[16].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[17].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[18].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[19].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[1].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[20].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[21].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[22].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[23].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[24].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[25].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[26].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[27].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[28].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[29].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[2].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[30].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[31].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[32].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[33].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[34].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[35].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[36].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[37].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[38].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[39].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[3].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[40].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[41].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[42].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[43].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[44].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[45].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[46].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[47].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[4].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[5].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[6].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[7].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[8].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_tx_ready_cnt[9].tx_ready_Sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[0].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[1].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[2].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[3].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[4].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[5].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[6].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[7].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[8].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[9].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[10].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[0].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[11].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[0].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[1].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[2].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[3].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[4].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[5].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[6].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[7].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[8].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[9].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[10].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[1].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[11].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[0].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[1].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[2].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[3].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[4].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[5].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[6].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[7].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[8].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[9].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[10].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[2].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[11].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[0].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[1].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[2].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[3].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[4].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[5].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[6].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[7].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[8].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[9].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[10].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \g_gbt_bank[3].gbtbank /i_gbt_bank/mgt_inst/\g_mgt_channel[11].i_mgt_ip_rx_buf /i_reset_tx_done_sync. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[9].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[10].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[11].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[12].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[13].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[0].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[1].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[2].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[3].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[4].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[5].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[6].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[7].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[8].RAM /BRAM_h. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/i_ram_cntr. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for stat_regs_inst/i_ram_rate. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[0].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[1].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[2].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[3].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[4].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[5].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[6].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[7].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[8].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[9].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[10].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[11].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[12].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[13].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[14].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[15].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[16].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[17].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[18].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[19].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[20].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[21].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[22].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[23].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[24].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[25].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[26].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[27].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[28].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[29].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[30].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[31].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[32].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[33].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[34].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[35].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[36].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[37].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[38].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[39].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[40].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[41].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[42].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[43].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[44].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[45].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[46].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[8].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[9].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[10].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[11].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[12].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \SFP_GEN[47].ngFEC_module /\bram_array[13].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[0].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[1].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[2].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[3].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[4].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[5].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[6].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[7].RAM /BRAM_l. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for i_I2C_if/\I2C_array[8].RAM /BRAM_l. (constraint file auto generated constraint). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:09:14 ; elapsed = 00:08:26 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'axi_state_reg' in module 'AXI4_to_ipbus' INFO: [Synth 8-802] inferred FSM for state register 'sm_init_reg' in module 'ttc_mgt_example_init' INFO: [Synth 8-802] inferred FSM for state register 'sm_reset_all_reg' in module 'ttc_mgt_example_gtwiz_reset' INFO: [Synth 8-802] inferred FSM for state register 'sm_reset_tx_reg' in module 'ttc_mgt_example_gtwiz_reset' INFO: [Synth 8-802] inferred FSM for state register 'sm_reset_rx_reg' in module 'ttc_mgt_example_gtwiz_reset' INFO: [Synth 8-802] inferred FSM for state register 'prbs_lock_state_reg' in module 'prbs_chk' INFO: [Synth 8-802] inferred FSM for state register 'stateBitSlip_reg' in module 'lpgbtfpga_framealigner' INFO: [Synth 8-802] inferred FSM for state register 'sm_init_reg' in module 'mgt_ip_example_init' INFO: [Synth 8-802] inferred FSM for state register 'phase_aligner_state_reg' in module 'tx_phase_aligner_fsm' INFO: [Synth 8-802] inferred FSM for state register 'gen_drp_interface.drp_tx_pi_state_reg' in module 'tx_pi_ctrl' INFO: [Synth 8-802] inferred FSM for state register 'clkSlipProcess.state_reg' in module 'mgt_bitslipctrl' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mgt_framealigner_pattsearch' INFO: [Synth 8-802] inferred FSM for state register 'fe_status_reg' in module 'buffer_ngccm_jtag_com' INFO: [Synth 8-802] inferred FSM for state register 'c_state_reg' in module 'i2c_master_bit_ctrl' INFO: [Synth 8-802] inferred FSM for state register 'statemachine.c_state_reg' in module 'i2c_master_byte_ctrl' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__2' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__2' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__2' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__3' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__3' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__3' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__4' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__4' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__4' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__5' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__5' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__5' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__6' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__6' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__6' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__7' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__7' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__7' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__8' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__8' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__8' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__9' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__9' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__9' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__10' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__10' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__10' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__11' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__11' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__11' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__12' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__12' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__12' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__13' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__13' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__13' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__14' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__14' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__14' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__15' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__15' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__15' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__16' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__16' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__16' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__17' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__17' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__17' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__18' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__18' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__18' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__19' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__19' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__19' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__20' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__20' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__20' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__21' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__21' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__21' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__22' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__22' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__22' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__23' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__23' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__23' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__24' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__24' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__24' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__25' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__25' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__25' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__26' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__26' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__26' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__27' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__27' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__27' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__28' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__28' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__28' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__29' INFO: [Common 17-14] Message 'Synth 8-802' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 000 r_data | 100 | 010 r_abort | 010 | 100 w_data | 101 | 001 w_abort | 011 | 011 clearfifo | 000 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'axi_state_reg' using encoding 'sequential' in module 'AXI4_to_ipbus' INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"xpm_memory_base:/gen_wr_b.gen_word_narrow.mem_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "xpm_memory_base:/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "xpm_memory_base:/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ST_START | 00 | 00 ST_TX_WAIT | 01 | 01 ST_RX_WAIT | 10 | 10 ST_MONITOR | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sm_init_reg' using encoding 'sequential' in module 'ttc_mgt_example_init' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ST_RESET_TX_BRANCH | 000 | 000 ST_RESET_TX_PLL | 001 | 001 ST_RESET_TX_DATAPATH | 010 | 010 ST_RESET_TX_WAIT_LOCK | 011 | 011 ST_RESET_TX_WAIT_USERRDY | 100 | 100 ST_RESET_TX_WAIT_RESETDONE | 101 | 101 ST_RESET_TX_IDLE | 110 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sm_reset_tx_reg' using encoding 'sequential' in module 'ttc_mgt_example_gtwiz_reset' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ST_RESET_RX_BRANCH | 000 | 000 ST_RESET_RX_PLL | 001 | 001 ST_RESET_RX_DATAPATH | 010 | 010 ST_RESET_RX_WAIT_LOCK | 011 | 011 ST_RESET_RX_WAIT_CDR | 100 | 100 ST_RESET_RX_WAIT_USERRDY | 101 | 101 ST_RESET_RX_WAIT_RESETDONE | 110 | 110 ST_RESET_RX_IDLE | 111 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sm_reset_rx_reg' using encoding 'sequential' in module 'ttc_mgt_example_gtwiz_reset' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ST_RESET_ALL_BRANCH | 000 | 001 ST_RESET_ALL_TX_PLL | 001 | 010 ST_RESET_ALL_TX_PLL_WAIT | 010 | 011 ST_RESET_ALL_RX_DP | 011 | 100 ST_RESET_ALL_RX_PLL | 100 | 101 ST_RESET_ALL_RX_WAIT | 101 | 110 iSTATE | 110 | 111 ST_RESET_ALL_INIT | 111 | 000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sm_reset_all_reg' using encoding 'sequential' in module 'ttc_mgt_example_gtwiz_reset' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- hunt | 10 | 00 going_lock | 11 | 01 lock | 01 | 10 going_hunt | 00 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'prbs_lock_state_reg' using encoding 'sequential' in module 'prbs_chk' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- e0_idle | 001 | 00 e4_dobitslip | 010 | 01 e5_waitncycles | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'stateBitSlip_reg' using encoding 'one-hot' in module 'lpgbtfpga_framealigner' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ST_START | 00 | 00 ST_TX_WAIT | 01 | 01 ST_RX_WAIT | 10 | 10 ST_MONITOR | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sm_init_reg' using encoding 'sequential' in module 'mgt_ip_example_init' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0110 | 0000 coarse_set_config | 1010 | 0001 coarse_shift_pi | 0010 | 0010 coarse_wait_pd | 0000 | 0011 fine_set_config | 0001 | 0100 fine_check_direction | 0011 | 0101 fine_shift_pi | 1101 | 0110 fine_wait_pd | 1011 | 0111 fine_aligned | 1100 | 1000 ui_set_offset | 1110 | 1001 ui_check_shift_pi | 1001 | 1010 ui_shift_pi | 1000 | 1011 ui_reset_tx | 0111 | 1100 aligned_clear_pd | 0100 | 1101 aligned_wait_pd | 0101 | 1110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'phase_aligner_state_reg' using encoding 'sequential' in module 'tx_phase_aligner_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0100 | 0000 phase_accu | 0101 | 0001 pre_register_0phase_drp | 0011 | 0010 wait_pre_register_0phase_drp | 0000 | 0011 register_1phase_drp | 0001 | 0100 wait_register_1phase_drp | 0010 | 0101 register_0phase_drp | 1000 | 0110 wait_register_0phase_drp | 0110 | 0111 done_drp | 0111 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_drp_interface.drp_tx_pi_state_reg' using encoding 'sequential' in module 'tx_pi_ctrl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- e0_idle | 001 | 00 e4_dobitslip | 010 | 01 e5_waitncycles | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'clkSlipProcess.state_reg' using encoding 'one-hot' in module 'mgt_bitslipctrl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- unlocked | 00 | 00 going_lock | 01 | 01 locked | 10 | 10 going_unlock | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mgt_framealigner_pattsearch' INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"xpm_memory_base__parameterized0:/gen_wr_b.gen_word_narrow.mem_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "xpm_memory_base__parameterized0:/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "xpm_memory_base__parameterized0:/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "xpm_memory_base__parameterized0:/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle_s | 000 | 000 write_s | 001 | 011 wait_s | 010 | 100 precmd_s | 011 | 101 cmd_s | 100 | 110 busy_s | 101 | 001 response_s | 110 | 010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fe_status_reg' using encoding 'sequential' in module 'buffer_ngccm_jtag_com' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle_b | 00000 | 00001 idle_c | 00001 | 00010 idle_d | 00010 | 00011 idle_e | 00011 | 00100 idle_f | 00100 | 00101 start_a | 00101 | 00110 start_b | 00110 | 00111 start_c | 00111 | 01000 start_d | 01000 | 01001 start_e | 01001 | 01010 stop_a | 01010 | 01011 stop_b | 01011 | 01100 stop_c | 01100 | 01101 stop_d | 01101 | 01110 stop_e | 01110 | 01111 wr_a | 01111 | 10101 wr_b | 10000 | 10110 wr_c | 10001 | 10111 wr_d | 10010 | 11000 wr_e | 10011 | 11001 rd_a | 10100 | 10000 rd_b | 10101 | 10001 rd_c | 10110 | 10010 rd_d | 10111 | 10011 rd_e | 11000 | 10100 idle_a | 11001 | 00000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'c_state_reg' using encoding 'sequential' in module 'i2c_master_bit_ctrl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 000 | 000 st_start | 001 | 001 st_read | 010 | 010 st_write | 011 | 011 st_ack | 100 | 100 st_stop | 101 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'statemachine.c_state_reg' using encoding 'sequential' in module 'i2c_master_byte_ctrl' INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"RAM:/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "RAM:/memory_reg" --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__4' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__4' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__4' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__5' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__5' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__5' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__6' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__6' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__6' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__7' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__7' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__7' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__8' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__8' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__8' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__9' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__9' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__9' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__10' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__10' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__10' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__11' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__11' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__11' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__12' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__12' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__12' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__13' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__13' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__13' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__14' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__14' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__14' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__15' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__15' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__15' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__16' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__16' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__16' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__17' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__17' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__17' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__18' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__18' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__18' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__19' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__19' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__19' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__20' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__20' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__20' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__21' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__21' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__21' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__22' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__22' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__22' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__23' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__23' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__23' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__24' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__24' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__24' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__25' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__25' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__25' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__26' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__26' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__26' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__27' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__27' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__27' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__28' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__28' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__28' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__29' INFO: [Common 17-14] Message 'Synth 8-3354' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:11:34 ; elapsed = 00:10:53 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Common 17-14] Message 'Synth 8-5775' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1363 21 Input 32 Bit Adders := 48 2 Input 16 Bit Adders := 146 2 Input 15 Bit Adders := 48 2 Input 12 Bit Adders := 1459 2 Input 11 Bit Adders := 1410 2 Input 10 Bit Adders := 4 2 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 733 2 Input 7 Bit Adders := 49 3 Input 7 Bit Adders := 48 2 Input 6 Bit Adders := 147 3 Input 6 Bit Adders := 48 2 Input 5 Bit Adders := 145 2 Input 4 Bit Adders := 834 2 Input 3 Bit Adders := 785 +---XORs : 2 Input 256 Bit XORs := 1 2 Input 234 Bit XORs := 1 2 Input 206 Bit XORs := 1 2 Input 44 Bit XORs := 48 3 Input 40 Bit XORs := 4 2 Input 40 Bit XORs := 48 3 Input 39 Bit XORs := 8 2 Input 20 Bit XORs := 48 3 Input 19 Bit XORs := 4 5 Input 19 Bit XORs := 4 5 Input 9 Bit XORs := 4 31 Input 5 Bit XORs := 2 2 Input 5 Bit XORs := 230 5 Input 4 Bit XORs := 1 2 Input 4 Bit XORs := 144 3 Input 2 Bit XORs := 1 5 Input 2 Bit XORs := 4 2 Input 1 Bit XORs := 110019 5 Input 1 Bit XORs := 22660 3 Input 1 Bit XORs := 19070 6 Input 1 Bit XORs := 4228 4 Input 1 Bit XORs := 11040 7 Input 1 Bit XORs := 1536 +---Registers : 256 Bit Registers := 3 234 Bit Registers := 5 206 Bit Registers := 1 120 Bit Registers := 48 100 Bit Registers := 48 84 Bit Registers := 288 60 Bit Registers := 3 58 Bit Registers := 9 53 Bit Registers := 1 51 Bit Registers := 3 49 Bit Registers := 1 48 Bit Registers := 194 33 Bit Registers := 2 32 Bit Registers := 11564 24 Bit Registers := 96 23 Bit Registers := 2 21 Bit Registers := 576 20 Bit Registers := 145 16 Bit Registers := 194 15 Bit Registers := 48 12 Bit Registers := 3493 11 Bit Registers := 1411 10 Bit Registers := 3 9 Bit Registers := 6 8 Bit Registers := 4394 7 Bit Registers := 1267 6 Bit Registers := 148 5 Bit Registers := 242 4 Bit Registers := 4511 3 Bit Registers := 2148 2 Bit Registers := 735 1 Bit Registers := 33165 +---RAMs : 64K Bit (2048 X 32 bit) RAMs := 681 32K Bit (1024 X 32 bit) RAMs := 48 16K Bit (512 X 32 bit) RAMs := 683 +---Muxes : 2 Input 256 Bit Muxes := 5 2 Input 234 Bit Muxes := 8 2 Input 230 Bit Muxes := 2 2 Input 206 Bit Muxes := 3 2 Input 145 Bit Muxes := 1 2 Input 128 Bit Muxes := 1 2 Input 100 Bit Muxes := 48 2 Input 84 Bit Muxes := 96 2 Input 60 Bit Muxes := 97 2 Input 58 Bit Muxes := 3 2 Input 52 Bit Muxes := 3 2 Input 48 Bit Muxes := 2 3 Input 48 Bit Muxes := 1 2 Input 44 Bit Muxes := 96 2 Input 40 Bit Muxes := 4 2 Input 39 Bit Muxes := 4 2 Input 33 Bit Muxes := 1 2 Input 32 Bit Muxes := 16548 5 Input 32 Bit Muxes := 3846 6 Input 32 Bit Muxes := 633 3 Input 32 Bit Muxes := 96 4 Input 32 Bit Muxes := 48 7 Input 32 Bit Muxes := 240 15 Input 32 Bit Muxes := 48 52 Input 32 Bit Muxes := 1 2 Input 31 Bit Muxes := 48 2 Input 23 Bit Muxes := 4 2 Input 21 Bit Muxes := 384 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 4 4 Input 16 Bit Muxes := 48 7 Input 16 Bit Muxes := 48 2 Input 16 Bit Muxes := 2 4 Input 15 Bit Muxes := 48 2 Input 12 Bit Muxes := 3157 7 Input 12 Bit Muxes := 96 2 Input 11 Bit Muxes := 4086 7 Input 11 Bit Muxes := 96 2 Input 10 Bit Muxes := 97 6 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 4 2 Input 8 Bit Muxes := 14529 5 Input 8 Bit Muxes := 633 8 Input 8 Bit Muxes := 9 6 Input 8 Bit Muxes := 3 4 Input 7 Bit Muxes := 49 2 Input 7 Bit Muxes := 48 4 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 147 3 Input 6 Bit Muxes := 97 2 Input 5 Bit Muxes := 56 4 Input 5 Bit Muxes := 48 32 Input 5 Bit Muxes := 585 2 Input 4 Bit Muxes := 3257 16 Input 4 Bit Muxes := 192 5 Input 4 Bit Muxes := 48 15 Input 4 Bit Muxes := 96 9 Input 4 Bit Muxes := 48 4 Input 4 Bit Muxes := 586 6 Input 4 Bit Muxes := 585 7 Input 4 Bit Muxes := 48 7 Input 3 Bit Muxes := 2 2 Input 3 Bit Muxes := 21681 8 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 682 5 Input 3 Bit Muxes := 633 12 Input 3 Bit Muxes := 96 15 Input 3 Bit Muxes := 585 6 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 827 2 Input 2 Bit Muxes := 3404 6 Input 2 Bit Muxes := 3 5 Input 2 Bit Muxes := 633 3 Input 2 Bit Muxes := 48 2 Input 1 Bit Muxes := 37964 4 Input 1 Bit Muxes := 3653 7 Input 1 Bit Muxes := 1213 8 Input 1 Bit Muxes := 26 6 Input 1 Bit Muxes := 3538 5 Input 1 Bit Muxes := 3943 3 Input 1 Bit Muxes := 8611 15 Input 1 Bit Muxes := 144 9 Input 1 Bit Muxes := 48 26 Input 1 Bit Muxes := 4095 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 5520 (col length:120) BRAMs: 4320 (col length: RAMB18 240 RAMB36 120) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3917] design gbt_bankx12__GCB0 has port TX_PHALIGNED_o[0] driven by constant 1 WARNING: [Synth 8-3917] design gbt_bankx12__GCB0 has port TX_PHCOMPUTED_o[0] driven by constant 1 WARNING: [Synth 8-3917] design gbt_bankx12__parameterized0__GCB0 has port TX_PHALIGNED_o[0] driven by constant 1 WARNING: [Synth 8-3917] design gbt_bankx12__parameterized0__GCB0 has port TX_PHCOMPUTED_o[0] driven by constant 1 WARNING: [Synth 8-3917] design gbt_bankx12__parameterized1__GCB0 has port TX_PHALIGNED_o[0] driven by constant 1 WARNING: [Synth 8-3917] design gbt_bankx12__parameterized1__GCB0 has port TX_PHCOMPUTED_o[0] driven by constant 1 WARNING: [Synth 8-3917] design gbt_bankx12__parameterized2__GCB0 has port TX_PHALIGNED_o[0] driven by constant 1 WARNING: [Synth 8-3917] design gbt_bankx12__parameterized2__GCB0 has port TX_PHCOMPUTED_o[0] driven by constant 1 WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[0].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[0].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[2].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[2].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[4].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[4].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[7].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[7].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[9].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[9].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[10].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[10].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[11].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[11].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[14].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[14].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[15].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[15].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[17].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[17].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[18].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[18].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[20].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[20].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[22].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[22].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[24].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[24].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[25].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[25].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[26].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[26].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[27].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[27].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[28].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[28].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[29].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[29].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[32].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[32].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[34].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[34].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[35].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[35].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[37].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[37].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[38].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[38].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[39].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[39].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[40].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[40].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[41].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[41].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[42].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[42].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[43].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[43].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[44].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[44].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[45].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[45].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[47].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[47].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-6014] Unused sequential element gen_wr_b.gen_word_narrow.mem_reg was removed. WARNING: [Synth 8-6014] Unused sequential element gen_wr_b.gen_word_narrow.mem_reg was removed. INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg" INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[3][3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[9].ngccm_status_reg_reg[9][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[8].ngccm_status_reg_reg[8][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[1].ngccm_status_reg_reg[1][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[0].ngccm_status_reg_reg[0][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[11].ngccm_status_reg_reg[11][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[10].ngccm_status_reg_reg[10][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[3].ngccm_status_reg_reg[3][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[2].ngccm_status_reg_reg[2][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[25].ngccm_status_reg_reg[25][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[24].ngccm_status_reg_reg[24][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[17].ngccm_status_reg_reg[17][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[16].ngccm_status_reg_reg[16][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[13].ngccm_status_reg_reg[13][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[12].ngccm_status_reg_reg[12][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[5].ngccm_status_reg_reg[5][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[4].ngccm_status_reg_reg[4][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[27].ngccm_status_reg_reg[27][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[26].ngccm_status_reg_reg[26][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[19].ngccm_status_reg_reg[19][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngccm_status_reg_reg[18][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[41].ngccm_status_reg_reg[41][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[40].ngccm_status_reg_reg[40][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[33].ngccm_status_reg_reg[33][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[32].ngccm_status_reg_reg[32][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[15].ngccm_status_reg_reg[15][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[14].ngccm_status_reg_reg[14][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[7].ngccm_status_reg_reg[7][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[6].ngccm_status_reg_reg[6][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[29].ngccm_status_reg_reg[29][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[28].ngccm_status_reg_reg[28][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[21].ngccm_status_reg_reg[21][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[20].ngccm_status_reg_reg[20][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[43].ngccm_status_reg_reg[43][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[42].ngccm_status_reg_reg[42][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[35].ngccm_status_reg_reg[35][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[34].ngccm_status_reg_reg[34][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[31].ngccm_status_reg_reg[31][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[30].ngccm_status_reg_reg[30][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[23].ngccm_status_reg_reg[23][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[45].ngccm_status_reg_reg[45][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[44].ngccm_status_reg_reg[44][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[37].ngccm_status_reg_reg[37][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[36].ngccm_status_reg_reg[36][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[47].ngccm_status_reg_reg[47][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[46].ngccm_status_reg_reg[46][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[39].ngccm_status_reg_reg[39][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[38].ngccm_status_reg_reg[38][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][25] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][26] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][27] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][28] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][30] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[153][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[152][25] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[152][26] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[152][27] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[152][28] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[152][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[152][30] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[152][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[152][9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[152][10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[152][11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[152][12] ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v:102] INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[32].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[32].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v:102] WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v:102] INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[37].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[37].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[17].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[17].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[17].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /\IPbus_DataOut_reg[31] ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v:102] WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v:102] INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[29].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[29].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[7].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[7].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v:102] WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v:102] INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[34].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[34].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[12].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[12].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v:102] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[46].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[46].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[36].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[36].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[33].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[33].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[31].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[31].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[30].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[30].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[23].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[23].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[21].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[21].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[19].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[19].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[16].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[16].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[13].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[13].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[12].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[12].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[8].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[8].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[6].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[6].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[5].i_rate_test_comm/rate_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] WARNING: [Synth 8-3936] Found unconnected internal register 'g_clock_rate_din[5].i_rate_test_comm/rate_i_reg' and it is trimmed from '24' to '16' bits. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd:63] INFO: [Common 17-14] Message 'Synth 8-3936' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-7129] Port ipb_clk in module ipbus_fabric is either unconnected or has no load WARNING: [Synth 8-7129] Port rst in module ipbus_fabric is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][31] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][30] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][29] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][28] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][27] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][26] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][25] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][24] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][23] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][22] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][21] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][20] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][19] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][18] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][17] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][16] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][15] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][14] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][13] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][12] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][11] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][10] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][9] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][8] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_mosi_i[ipb_addr][7] in module ipb_user_control_regs is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2561 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2560 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2563 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2562 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2565 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2564 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2567 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2566 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2569 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2568 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2571 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2570 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2573 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2572 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2575 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2574 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2577 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2576 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2579 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2578 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2581 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2580 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2583 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2582 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2585 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2584 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2587 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2586 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2589 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2588 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__2590 is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single__parameterized2__1048 is either unconnected or has no load WARNING: [Synth 8-7129] Port jtag_reg_i[11] in module LocalJTAGBridge__xdcDup__19 is either unconnected or has no load WARNING: [Synth 8-7129] Port jtag_reg_i[10] in module LocalJTAGBridge__xdcDup__19 is either unconnected or has no load WARNING: [Synth 8-7129] Port tms_i in module LocalJTAGBridge__xdcDup__19 is either unconnected or has no load WARNING: [Synth 8-7129] Port trst_i in module LocalJTAGBridge__xdcDup__19 is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_local[3] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[31] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[30] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[29] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[28] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[27] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[26] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[25] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[24] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[23] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[22] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[21] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[20] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[19] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[18] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[17] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[16] in module LocalI2CBridge__152 is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_local[3] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[31] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[30] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[29] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[28] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[27] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[26] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[25] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[24] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[23] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[22] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[21] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[20] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[19] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[18] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[17] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[16] in module LocalI2CBridge__151 is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_local[3] in module LocalI2CBridge__150 is either unconnected or has no load WARNING: [Synth 8-7129] Port DataIn_local[31] in module LocalI2CBridge__150 is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[18].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[18].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][0]' (FDP) to 'SFP_GEN[18].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][1]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][1]' (FDP) to 'SFP_GEN[18].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/TX_Word_tmp_reg[72]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/TX_Word_tmp_reg[76]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/TX_Word_tmp_reg[73]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/TX_Word_tmp_reg[77]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/TX_Word_tmp_reg[74]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/TX_Word_tmp_reg[76]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/TX_Word_tmp_reg[75]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/TX_Word_tmp_reg[77]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[22].ngccm_status_reg_reg[22][9]' (FDCE) to 'SFP_GEN[22].ngccm_status_reg_reg[22][31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[22].ngccm_status_reg_reg[22][10]' (FDCE) to 'SFP_GEN[22].ngccm_status_reg_reg[22][31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[22].ngccm_status_reg_reg[22][11]' (FDCE) to 'SFP_GEN[22].ngccm_status_reg_reg[22][31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[22].ngccm_status_reg_reg[22][12]' (FDCE) to 'SFP_GEN[22].ngccm_status_reg_reg[22][31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[22].ngccm_status_reg_reg[22][13]' (FDCE) to 'SFP_GEN[22].ngccm_status_reg_reg[22][31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[22].ngccm_status_reg_reg[22][14]' (FDCE) to 'SFP_GEN[22].ngccm_status_reg_reg[22][31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[22].ngccm_status_reg_reg[22][15]' (FDCE) to 'SFP_GEN[22].ngccm_status_reg_reg[22][31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[22].ngccm_status_reg_reg[22][25]' (FDCE) to 'SFP_GEN[22].ngccm_status_reg_reg[22][31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[22].ngccm_status_reg_reg[22][26]' (FDCE) to 'SFP_GEN[22].ngccm_status_reg_reg[22][31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[22].ngccm_status_reg_reg[22][27]' (FDCE) to 'SFP_GEN[22].ngccm_status_reg_reg[22][31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[22].ngccm_status_reg_reg[22][28]' (FDCE) to 'SFP_GEN[22].ngccm_status_reg_reg[22][31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[22].ngccm_status_reg_reg[22][29]' (FDCE) to 'SFP_GEN[22].ngccm_status_reg_reg[22][31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[22].ngccm_status_reg_reg[22][30]' (FDCE) to 'SFP_GEN[22].ngccm_status_reg_reg[22][31]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[22].ngccm_status_reg_reg[22][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\i_AXI4_to_ipbus/axi_out_reg[axi_rresp][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\i_AXI4_to_ipbus/axi_out_reg[axi_bresp][0] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\i_AXI4_to_ipbus/ipb_out_reg[ipb_addr][30] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\i_AXI4_to_ipbus/ipb_out_reg[ipb_addr][31] ) INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[16]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[17]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[18]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[19]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[20]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[21]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[22]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[23]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[24]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[25]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[26]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[27]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[28]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[29]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[30]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[0].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngCCM_gbt /\IPbus_gen[0].IPbus_local_inst /\IPbus_DataOut_reg[31] ) INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[16]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[17]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[18]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[19]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[20]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[21]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[22]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[23]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[24]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[25]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[26]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[27]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[28]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[29]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[30]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngCCM_gbt /\IPbus_gen[1].IPbus_local_inst /\IPbus_DataOut_reg[31] ) INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[16]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[17]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[18]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[19]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[20]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[21]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[22]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[23]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[24]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[25]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[26]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[27]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[28]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[29]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[30]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngCCM_gbt /\IPbus_gen[2].IPbus_local_inst /\IPbus_DataOut_reg[31] ) INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[16]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[17]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[18]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[19]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[20]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[21]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[22]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[23]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[24]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[25]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[26]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[27]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[28]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[29]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[30]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngCCM_gbt /\IPbus_gen[3].IPbus_local_inst /\IPbus_DataOut_reg[31] ) INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[16]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[17]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[18]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[19]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[20]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[21]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[22]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[23]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[24]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[25]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[26]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[27]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[28]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[29]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[30]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[4].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngCCM_gbt /\IPbus_gen[4].IPbus_local_inst /\IPbus_DataOut_reg[31] ) INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[5].IPbus_local_inst/IPbus_DataOut_reg[16]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[5].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[5].IPbus_local_inst/IPbus_DataOut_reg[17]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[5].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[5].IPbus_local_inst/IPbus_DataOut_reg[18]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[5].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[5].IPbus_local_inst/IPbus_DataOut_reg[19]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[5].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[5].IPbus_local_inst/IPbus_DataOut_reg[20]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[5].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Synth 8-3886] merging instance 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[5].IPbus_local_inst/IPbus_DataOut_reg[21]' (FDE) to 'SFP_GEN[18].ngCCM_gbt/IPbus_gen[5].IPbus_local_inst/IPbus_DataOut_reg[31]' INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngCCM_gbt /\IPbus_gen[5].IPbus_local_inst /\IPbus_DataOut_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngCCM_gbt /\IPbus_gen[6].IPbus_local_inst /\IPbus_DataOut_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngCCM_gbt /\IPbus_gen[7].IPbus_local_inst /\IPbus_DataOut_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngCCM_gbt /\IPbus_gen[8].IPbus_local_inst /\IPbus_DataOut_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngCCM_gbt /\IPbus_gen[9].IPbus_local_inst /\IPbus_DataOut_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngCCM_gbt /\IPbus_gen[10].IPbus_local_inst /\IPbus_DataOut_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngCCM_gbt /\IPbus_gen[11].IPbus_local_inst /\IPbus_DataOut_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\SFP_GEN[18].ngCCM_gbt /\IPbus_gen[13].IPbus_local_inst /\IPbus_DataOut_reg[23] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[114][8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[114][9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[114][10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[114][19] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[114][21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[114][23] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[114][24] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\stat_reg_reg[114][25] ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[13].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[13].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[23].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[23].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[9].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[9].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[40].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[40].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[15].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[15].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[46].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[46].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[6].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[6].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[43].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[43].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[1].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[1].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[3].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[3].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[20].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[20].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[4].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[4].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[30].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[30].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[8].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[8].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[36].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[36].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[28].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[28].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[13][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[12][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[11][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[10][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[9][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[8][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[7][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[6][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[5][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[4][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[3][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[2][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[1][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ipb_miso[0][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[31] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[30] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[29] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[28] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[27] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[26] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[25] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[24] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[23] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[21] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[19] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[10] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[9] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngccm_bkp_regs[8] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngCCM_status_o[14] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngCCM_status_o[13] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngCCM_status_o[12] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngCCM_status_o[11] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngCCM_status_o[10] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__28 has port ngCCM_status_o[9] driven by constant 0 INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[13][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[12][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[11][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[10][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[9][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[8][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[7][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[6][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[5][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[4][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[3][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[2][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[1][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ipb_miso[0][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[31] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[30] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[29] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[28] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[27] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[26] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[25] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[24] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[23] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[21] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[19] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[10] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[9] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngccm_bkp_regs[8] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngCCM_status_o[14] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngCCM_status_o[13] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngCCM_status_o[12] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngCCM_status_o[11] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngCCM_status_o[10] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__6 has port ngCCM_status_o[9] driven by constant 0 INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[13][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[12][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[11][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[10][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[9][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[8][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[7][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[6][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[5][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[4][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[3][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[2][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[1][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ipb_miso[0][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ngccm_bkp_regs[31] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ngccm_bkp_regs[30] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ngccm_bkp_regs[29] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ngccm_bkp_regs[28] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ngccm_bkp_regs[27] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ngccm_bkp_regs[26] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ngccm_bkp_regs[25] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ngccm_bkp_regs[24] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ngccm_bkp_regs[23] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__1 has port ngccm_bkp_regs[21] driven by constant 0 INFO: [Common 17-14] Message 'Synth 8-3917' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[35].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[35].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[41].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[41].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[2].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[2].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[33].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[33].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[10].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[10].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[26].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[26].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[16].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[16].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[11].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[11].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[47].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[47].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[44].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[44].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[14].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[14].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[38].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[38].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Common 17-14] Message 'Synth 8-3917' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[45].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[45].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[19].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[19].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[22].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[22].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[21].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[21].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[31].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[31].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[42].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[42].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" INFO: [Synth 8-5779] Default cascade height of 1 will be used for BRAM '"\SFP_GEN[39].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"'. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 32 for RAM "\SFP_GEN[39].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg" --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:17:50 ; elapsed = 00:17:20 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +------------------+---------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------------+---------------+---------------+----------------+ |rs_decoder_N31K29 | tmp | 32x5 | LUT | |rs_decoder_N31K29 | tmp | 32x5 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | +------------------+---------------+---------------+----------------+ Block RAM: Preliminary Mapping Report (see note below) +---------------------------------------------------------------------------------+--------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights | +---------------------------------------------------------------------------------+--------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base__parameterized0: | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base: | gen_wr_b.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | R | 512 x 32(NO_CHANGE) | W | R | Port A and B | 0 | 1 | 1 | |stat_regs_inst/i_ram_rate/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | R | 512 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[32].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[37].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[17].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[29].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[7].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[34].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[12].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[18].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[13].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[23].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[9].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[40].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[15].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[46].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[6].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[43].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[1].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[3].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[20].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[4].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[30].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[8].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[36].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[28].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[35].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[41].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[2].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[33].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[10].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[26].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[16].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[11].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[47].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[44].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[14].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[38].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[45].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[19].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[22].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[21].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[31].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[42].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[39].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | +---------------------------------------------------------------------------------+--------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- WARNING: [Synth 8-3321] set_multicycle_path : Empty from list for constraint at line 152 of D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:152] WARNING: [Synth 8-3321] set_multicycle_path : Empty to list for constraint at line 152 of D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:152] WARNING: [Synth 8-3321] set_multicycle_path : Empty from list for constraint at line 154 of D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:154] WARNING: [Synth 8-3321] set_multicycle_path : Empty to list for constraint at line 154 of D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:154] WARNING: [Synth 8-3321] set_multicycle_path : Empty from list for constraint at line 156 of D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:156] WARNING: [Synth 8-3321] set_multicycle_path : Empty to list for constraint at line 156 of D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:156] --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:18:57 ; elapsed = 00:18:32 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 14 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 18 for RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" INFO: [Common 17-14] Message 'Synth 8-7030' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-3971] The signal "\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" was recognized as a true dual port RAM template. INFO: [Common 17-14] Message 'Synth 8-3971' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Synth 8-5556] The block RAM "\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg" may be mapped as a cascade chain, because it is not timing critical. INFO: [Common 17-14] Message 'Synth 8-5556' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:24:22 ; elapsed = 00:23:58 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +----------------------------------------------------------------------------------------------------------+--------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights | +----------------------------------------------------------------------------------------------------------+--------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[0].ngFEC_modulei_59 /\SFP_GEN[0].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[0].ngFEC_modulei_59 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[1].ngFEC_modulei_60 /\SFP_GEN[1].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[1].ngFEC_modulei_60 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[2].ngFEC_modulei_61 /\SFP_GEN[2].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[2].ngFEC_modulei_61 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[3].ngFEC_modulei_62 /\SFP_GEN[3].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[3].ngFEC_modulei_62 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[4].ngFEC_modulei_63 /\SFP_GEN[4].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[4].ngFEC_modulei_63 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[5].ngFEC_modulei_64 /\SFP_GEN[5].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[5].ngFEC_modulei_64 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[6].ngFEC_modulei_65 /\SFP_GEN[6].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[6].ngFEC_modulei_65 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[7].ngFEC_modulei_66 /\SFP_GEN[7].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[7].ngFEC_modulei_66 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[8].ngFEC_modulei_67 /\SFP_GEN[8].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[8].ngFEC_modulei_67 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[9].ngFEC_modulei_68 /\SFP_GEN[9].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[9].ngFEC_modulei_68 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[10].ngFEC_modulei_69 /\SFP_GEN[10].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[10].ngFEC_modulei_69 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[11].ngFEC_modulei_70 /\SFP_GEN[11].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[11].ngFEC_modulei_70 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[12].ngFEC_modulei_71 /\SFP_GEN[12].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[12].ngFEC_modulei_71 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[13].ngFEC_modulei_72 /\SFP_GEN[13].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[13].ngFEC_modulei_72 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[14].ngFEC_modulei_73 /\SFP_GEN[14].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[14].ngFEC_modulei_73 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[15].ngFEC_modulei_74 /\SFP_GEN[15].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[15].ngFEC_modulei_74 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[16].ngFEC_modulei_75 /\SFP_GEN[16].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[16].ngFEC_modulei_75 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[17].ngFEC_modulei_76 /\SFP_GEN[17].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[17].ngFEC_modulei_76 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[18].ngFEC_modulei_77 /\SFP_GEN[18].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[18].ngFEC_modulei_77 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[19].ngFEC_modulei_78 /\SFP_GEN[19].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[19].ngFEC_modulei_78 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[20].ngFEC_modulei_79 /\SFP_GEN[20].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[20].ngFEC_modulei_79 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[21].ngFEC_modulei_80 /\SFP_GEN[21].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[21].ngFEC_modulei_80 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[22].ngFEC_modulei_81 /\SFP_GEN[22].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[22].ngFEC_modulei_81 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[23].ngFEC_modulei_82 /\SFP_GEN[23].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[23].ngFEC_modulei_82 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[24].ngFEC_modulei_83 /\SFP_GEN[24].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[24].ngFEC_modulei_83 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[25].ngFEC_modulei_84 /\SFP_GEN[25].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[25].ngFEC_modulei_84 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[26].ngFEC_modulei_85 /\SFP_GEN[26].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[26].ngFEC_modulei_85 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[27].ngFEC_modulei_86 /\SFP_GEN[27].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[27].ngFEC_modulei_86 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[28].ngFEC_modulei_87 /\SFP_GEN[28].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[28].ngFEC_modulei_87 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[29].ngFEC_modulei_88 /\SFP_GEN[29].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[29].ngFEC_modulei_88 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[30].ngFEC_modulei_89 /\SFP_GEN[30].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[30].ngFEC_modulei_89 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[31].ngFEC_modulei_90 /\SFP_GEN[31].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[31].ngFEC_modulei_90 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[32].ngFEC_modulei_91 /\SFP_GEN[32].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[32].ngFEC_modulei_91 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[33].ngFEC_modulei_92 /\SFP_GEN[33].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[33].ngFEC_modulei_92 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[34].ngFEC_modulei_93 /\SFP_GEN[34].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[34].ngFEC_modulei_93 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[35].ngFEC_modulei_94 /\SFP_GEN[35].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[35].ngFEC_modulei_94 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[36].ngFEC_modulei_95 /\SFP_GEN[36].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[36].ngFEC_modulei_95 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[37].ngFEC_modulei_96 /\SFP_GEN[37].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[37].ngFEC_modulei_96 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[38].ngFEC_modulei_97 /\SFP_GEN[38].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[38].ngFEC_modulei_97 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[39].ngFEC_modulei_98 /\SFP_GEN[39].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[39].ngFEC_modulei_98 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[40].ngFEC_modulei_99 /\SFP_GEN[40].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[40].ngFEC_modulei_99 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[41].ngFEC_modulei_100 /\SFP_GEN[41].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[41].ngFEC_modulei_100 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[42].ngFEC_modulei_101 /\SFP_GEN[42].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[42].ngFEC_modulei_101 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[43].ngFEC_modulei_102 /\SFP_GEN[43].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[43].ngFEC_modulei_102 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[44].ngFEC_modulei_103 /\SFP_GEN[44].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[44].ngFEC_modulei_103 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[45].ngFEC_modulei_104 /\SFP_GEN[45].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[45].ngFEC_modulei_104 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[46].ngFEC_modulei_105 /\SFP_GEN[46].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[46].ngFEC_modulei_105 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |\SFP_GEN[47].ngFEC_modulei_106 /\SFP_GEN[47].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\SFP_GEN[47].ngFEC_modulei_106 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |i_I2C_ifi_107/\i_I2C_if/I2C_array[0].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[0].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |i_I2C_ifi_107/\i_I2C_if/I2C_array[1].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[1].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |i_I2C_ifi_107/\i_I2C_if/I2C_array[2].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[2].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |i_I2C_ifi_107/\i_I2C_if/I2C_array[3].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[3].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |i_I2C_ifi_107/\i_I2C_if/I2C_array[4].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[4].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |i_I2C_ifi_107/\i_I2C_if/I2C_array[5].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[5].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |i_I2C_ifi_107/\i_I2C_if/I2C_array[6].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[6].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |i_I2C_ifi_107/\i_I2C_if/I2C_array[7].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[7].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |i_I2C_ifi_107/\i_I2C_if/I2C_array[8].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg | 2 K x 32(NO_CHANGE) | W | R | 2 K x 32(NO_CHANGE) | W | R | Port A and B | 0 | 2 | 1,1 | |\I2C_array[8].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | | 512 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | | |xpm_memory_base: | gen_wr_b.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | R | 512 x 32(NO_CHANGE) | W | R | Port A and B | 0 | 1 | 1 | |stat_regs_inst/i_ram_rate/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 512 x 32(NO_CHANGE) | W | R | 512 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[32].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[37].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[17].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[29].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[7].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[34].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[12].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[18].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[13].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[23].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[9].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[40].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[15].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[46].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[6].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[43].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[1].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[3].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[20].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[4].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[30].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[8].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[36].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[28].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[35].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[41].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[2].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[33].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[10].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[26].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[16].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[11].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[47].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[44].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[14].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[38].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[45].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[19].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[22].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[21].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[31].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[42].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | |\SFP_GEN[39].ngCCM_gbt /LocalJTAGBridge_inst | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 1 | +----------------------------------------------------------------------------------------------------------+--------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[6].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[6].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[6].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[6].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[10].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[10].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[10].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[10].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngFEC_modulei_59/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance SFP_GEN[1].ngFEC_modulei_60/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:29:44 ; elapsed = 00:29:36 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred:in0 to constant 0 INFO: [Common 17-14] Message 'Synth 8-3295' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:45:16 ; elapsed = 00:45:33 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:45:19 ; elapsed = 00:45:36 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:49:50 ; elapsed = 00:50:07 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:50:04 ; elapsed = 00:50:22 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:50:29 ; elapsed = 00:50:47 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:50:34 ; elapsed = 00:50:52 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+---------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+---------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |ngFEC_top | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/reset_tx_pipe_reg[4] | 5 | 48 | NO | NO | YES | 48 | 0 | |ngFEC_top | stat_regs_inst/clk_phase_reg[6] | 3 | 1 | NO | NO | YES | 1 | 0 | |ngFEC_top | stat_regs_inst/clk_phase_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | |ngFEC_top | fabric_clk_div2_q_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | +------------+---------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+---------------------+----------+ | |BlackBox name |Instances | +------+---------------------+----------+ |1 |mgt_ip | 48| |2 |axi_chip2chip_64B66B | 1| |3 |aurora_64b66b_0 | 1| |4 |ttc_mgt | 1| +------+---------------------+----------+ Report Cell Usage: +------+--------------------------+-------+ | |Cell |Count | +------+--------------------------+-------+ |1 |aurora_64b66b_0_bbox | 1| |2 |axi_chip2chip_64B66B_bbox | 1| |3 |mgt_ip_bbox | 1| |4 |mgt_ip_bbox_3_ | 47| |51 |ttc_mgt_bbox | 1| |52 |BUFG | 8| |53 |BUFGCE_DIV | 1| |54 |BUFG_GT | 3| |55 |CARRY8 | 8572| |56 |DSP_ALU | 1003| |61 |DSP_A_B_DATA | 1003| |63 |DSP_C_DATA | 1003| |65 |DSP_MULTIPLIER | 1003| |67 |DSP_M_DATA | 1003| |69 |DSP_OUTPUT | 1003| |72 |DSP_PREADD | 1003| |73 |DSP_PREADD_DATA | 1003| |77 |IBUFDS_GTE3 | 6| |78 |LUT1 | 28953| |79 |LUT2 | 65098| |80 |LUT3 | 103834| |81 |LUT4 | 100558| |82 |LUT5 | 92130| |83 |LUT6 | 149382| |84 |MMCME3_ADV | 1| |85 |MMCME3_BASE | 1| |86 |MUXF7 | 1057| |87 |RAMB18E2 | 681| |88 |RAMB36E2 | 1412| |92 |SRL16E | 116| |93 |FDCE | 188843| |94 |FDPE | 17646| |95 |FDRE | 164666| |96 |FDSE | 4632| |97 |IBUF | 16| |98 |IOBUF | 18| |99 |OBUF | 10| |100 |OBUFDS_GTE3 | 1| +------+--------------------------+-------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:50:37 ; elapsed = 00:50:54 . Memory (MB): peak = 7969.586 ; gain = 6754.422 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 814 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:42:25 ; elapsed = 00:44:06 . Memory (MB): peak = 7969.586 ; gain = 767.508 Synthesis Optimization Complete : Time (s): cpu = 00:50:37 ; elapsed = 00:50:56 . Memory (MB): peak = 7969.586 ; gain = 6754.422 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 7969.586 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 10676 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 20 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-441] Inserted BUFG_GT_SYNC BUFG_GT_SYNC for BUFG_GT i_refclk125_bufg Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.419 . Memory (MB): peak = 8830.828 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1046 instances were transformed. BUFG => BUFGCE: 8 instances DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 1003 instances IBUF => IBUF (IBUFCTRL, INBUF): 16 instances IOBUF => IOBUF (IBUFCTRL, INBUF, OBUFT): 18 instances MMCME3_BASE => MMCME3_ADV: 1 instance INFO: [Common 17-83] Releasing license: Synthesis 1518 Infos, 596 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:56:50 ; elapsed = 00:57:10 . Memory (MB): peak = 8830.828 ; gain = 7819.793 INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/synth_1/ngFEC_top.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:03:20 ; elapsed = 00:02:34 . Memory (MB): peak = 8830.828 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file ngFEC_top_utilization_synth.rpt -pb ngFEC_top_utilization_synth.pb report_utilization: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 8830.828 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Sat Mar 13 07:20:44 2021...