
ø
²The XPM instance: <%s> is part of IP: <%s>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
136*memdata2î
Ùi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst2default:default2/
i_axi_slave/i_axi_chip2chip2default:defaultZ28-208h px 
ø
²The XPM instance: <%s> is part of IP: <%s>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
136*memdata2î
Ùi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst2default:default2/
i_axi_slave/i_axi_chip2chip2default:defaultZ28-208h px 
§
½Found XPM memory block %s with a %s property set to %s. A value of %s is required. You will not be able to use the updatemem program to update the bitstream with new data for the %s block.
119*memdata2î
Ùi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst2default:default2&
P_MEMORY_PRIMITIVE2default:default2
distributed2default:default2
block2default:default2î
Ùi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst2default:defaultZ28-167h px 
ù
²The XPM instance: <%s> is part of IP: <%s>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
136*memdata2ï
Úi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst2default:default2/
i_axi_slave/i_axi_chip2chip2default:defaultZ28-208h px 
ù
²The XPM instance: <%s> is part of IP: <%s>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
136*memdata2ï
Úi_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst2default:default2/
i_axi_slave/i_axi_chip2chip2default:defaultZ28-208h px 
‡
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2$
write_mem_info: 2default:default2
00:06:232default:default2
00:06:232default:default2
	16582.8752default:default2
0.0002default:defaultZ17-268h px 
i
Command: %s
53*	vivadotcl28
$write_bitstream -force ngFEC_top.bit2default:defaultZ4-113h px 
£
@Attempting to get a license for feature '%s' and/or device '%s'
308*common2"
Implementation2default:default2
xcku1152default:defaultZ17-347h px 
“
0Got license for feature '%s' and/or device '%s'
310*common2"
Implementation2default:default2
xcku1152default:defaultZ17-349h px 
Ñ
The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
719*common2
2021.012default:defaultZ17-1540h px 
x
,Running DRC as a precondition to command %s
1349*	planAhead2#
write_bitstream2default:defaultZ12-1349h px 
>
IP Catalog is up to date.1232*coregenZ19-1839h px 
P
Running DRC with %s threads
24*drc2
22default:defaultZ23-27h px 
Ë
‚Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.%s*DRC2(
 DRC|Pin Planning2default:default8ZCFGBVS-1h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0]2ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0]2ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0]2ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0]2ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0]2ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0]2ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0]2ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0]2ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0]2ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/A[29:0]2ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/B[17:0]2ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/C[47:0]2ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/A[29:0]2ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/B[17:0]2ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/C[47:0]2ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/A[29:0]2ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/B[17:0]2ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/C[47:0]2ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/A[29:0]2ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/B[17:0]2ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
î
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/C[47:0]2ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
›
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0]=ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
›
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0]=ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
›
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0]=ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
›
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0]=ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
›
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0]=ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
›
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0]=ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
›
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0]=ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
›
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0]=ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
›
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0]=ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ö
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2
 "†
:ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0]4ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ö
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2
 "†
:ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0]4ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ö
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2
 "†
:ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0]4ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[29:0]5ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[17:0]5ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[47:0]5ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[29:0]5ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[17:0]5ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[47:0]5ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[29:0]5ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[17:0]5ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[47:0]5ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[29:0]5ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[17:0]5ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[47:0]5ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[29:0]5ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[17:0]5ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
ú
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2Ÿ
 "ˆ
;ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[47:0]5ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0]>ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0]>ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
Ÿ
fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0]>ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPIP-2h px 
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Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2

DRC DPIP-22default:default2
1002default:defaultZ17-14h px 
±
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst2default:default2default:default2™
 "‚
8ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/P[47:0]2ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]=ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
â
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]>ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
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<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
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Dctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]>ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
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Dctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]>ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
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Dctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]>ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
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Dctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]>ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2±
 "š
Dctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]>ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]=ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]=ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]=ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]=ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]=ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]=ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]=ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]=ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2¯
 "˜
Cctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]=ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2
 "†
7stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst	7stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2§
 "
?stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst/P[47:0]9stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2É
 "²
Pstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]Jstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2É
 "²
Pstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0]Jstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2ë
 "Ô
astat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0][stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ö
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¡
 "Š
9stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst	9stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2«
 "”
Astat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0];stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
š
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2Ã
 "¬
Jstat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Jstat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2Í
 "¶
Rstat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0]Lstat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
š
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2Ã
 "¬
Jstat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Jstat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2Í
 "¶
Rstat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0]Lstat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
š
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2Ã
 "¬
Jstat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Jstat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2Í
 "¶
Rstat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0]Lstat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
š
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2Ã
 "¬
Jstat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Jstat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2Í
 "¶
Rstat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0]Lstat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2Ã
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Jstat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Jstat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2Í
 "¶
Rstat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0]Lstat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2Ã
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Jstat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Jstat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2Í
 "¶
Rstat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0]Lstat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
š
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2Ã
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Jstat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Jstat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2Í
 "¶
Rstat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0]Lstat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
š
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2Ã
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Jstat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Jstat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2Í
 "¶
Rstat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0]Lstat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2£
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:stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2­
 "–
Bstat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2/P[47:0]<stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
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<stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
â
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
â
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2±
 "š
Dstat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2/P[47:0]>stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Ú
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2­
 "–
Bstat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2/P[47:0]<stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2­
 "–
Bstat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2/P[47:0]<stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
Þ
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2¯
 "˜
Cstat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2/P[47:0]=stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E22default:default8ZDPOP-3h px 
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1002default:defaultZ17-14h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
×
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
×
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
×
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
×
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
×
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
ê
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
×
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
Õ
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
Õ
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
Õ
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
Õ
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
Õ
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
Õ
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
è
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
Õ
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
Õ
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
Õ
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
¾
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2|
 "f
'ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst	'ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
à
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2
 "†
7stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst	7stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
à
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2
 "†
7stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst	7stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
à
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2
 "†
7stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst	7stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
‚
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
‚
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
‚
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst	;stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
‚
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
‚
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
‚
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst	;stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
¤
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
¤
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
¤
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
Š
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2Ç
 "°
Lstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst	Lstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
¤
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
¤
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
¤
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
Š
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2Ç
 "°
Lstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst	Lstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
¤
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
¤
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
¤
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
Š
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2Ç
 "°
Lstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst	Lstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
¤
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
¤
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
¤
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
Š
ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2Ç
 "°
Lstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst	Lstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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ÝDSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell %s with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0%s*DRC2á
 "Ê
Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst	Ystat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst2default:default2default:default2C
 +DRC|Netlist|Instance|Register usage|DSP48E22default:default8ZDPREG-7h px 
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14*common2
DRC DPREG-72default:default2
1002default:defaultZ17-14h px 
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ŸIO Bus SLR Crossings: Bus port GBT_refclk1_n spans more than one Super Logic Region (SLR).   Bits placed in SLR 1:  3, 1.  
  Bits placed in SLR 0:  2, 0.  
%s*DRC23
 DRC|Pin Planning|Chip Level2default:default8ZIOBUSSLRC-1h px 
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ŸIO Bus SLR Crossings: Bus port GBT_refclk1_p spans more than one Super Logic Region (SLR).   Bits placed in SLR 1:  3, 1.  
  Bits placed in SLR 0:  2, 0.  
%s*DRC23
 DRC|Pin Planning|Chip Level2default:default8ZIOBUSSLRC-1h px 
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ÃIO Bus SLR Crossings: Bus port GBT_rxn spans more than one Super Logic Region (SLR).   Bits placed in SLR 1:  47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12.  
  Bits placed in SLR 0:  35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0.  
%s*DRC23
 DRC|Pin Planning|Chip Level2default:default8ZIOBUSSLRC-1h px 
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ÃIO Bus SLR Crossings: Bus port GBT_rxp spans more than one Super Logic Region (SLR).   Bits placed in SLR 1:  47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12.  
  Bits placed in SLR 0:  35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0.  
%s*DRC23
 DRC|Pin Planning|Chip Level2default:default8ZIOBUSSLRC-1h px 
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ÃIO Bus SLR Crossings: Bus port GBT_txn spans more than one Super Logic Region (SLR).   Bits placed in SLR 1:  47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12.  
  Bits placed in SLR 0:  35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0.  
%s*DRC23
 DRC|Pin Planning|Chip Level2default:default8ZIOBUSSLRC-1h px 
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ÃIO Bus SLR Crossings: Bus port GBT_txp spans more than one Super Logic Region (SLR).   Bits placed in SLR 1:  47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12.  
  Bits placed in SLR 0:  35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0.  
%s*DRC23
 DRC|Pin Planning|Chip Level2default:default8ZIOBUSSLRC-1h px 
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_No routable loads: 1 net(s) have no routable loads. The problem bus(es) and/or net(s) are %s.%s*DRC2¹
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„i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_assertion_r„i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_assertion_r2default:default2default:default2=
 %DRC|Implementation|Routing|Chip Level2default:default8Z	RTSTAT-10h px 
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ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
î
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
î
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
î
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
î
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
î
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
î
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ò
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ô
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ô
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ô
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ô
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ô
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
‡
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ô
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ò
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ò
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ò
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ò
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ò
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ò
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ò
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ò
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ò
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
Û
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2|
 "f
'ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst	'ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ý
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2
 "†
7stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst	7stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ý
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2
 "†
7stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst	7stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ý
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2
 "†
7stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst	7stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
Ÿ
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
Ÿ
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
Ÿ
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst	;stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
Ÿ
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
Ÿ
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
Ÿ
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
…
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst	;stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 

ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¡
 "Š
9stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst	9stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 

ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¡
 "Š
9stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst	9stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 

ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¡
 "Š
9stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst	9stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ù
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2™
 "‚
5stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst	5stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ù
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2™
 "‚
5stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst	5stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ù
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2™
 "‚
5stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst	5stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
™
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
™
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
™
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ý
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2
 "†
7stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst	7stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
™
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
™
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
™
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
ý
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2
 "†
7stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst	7stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
™
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
™
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
™
ðenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-155h px 
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Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
DRC AVAL-1552default:default2
1002default:defaultZ17-14h px 
á
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
á
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
á
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
á
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
á
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
á
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
á
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2Ž
 "x
0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst	0ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
å
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ç
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ç
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ç
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ç
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ç
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ú
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2§
 "
<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	<ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ç
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2”
 "~
3ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst	3ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
å
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
å
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
å
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
å
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
å
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
å
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
å
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
å
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst	;ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
å
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2’
 "|
2ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst	2ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
Î
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2|
 "f
'ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst	'ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ð
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2
 "†
7stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst	7stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ð
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2
 "†
7stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst	7stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ð
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2
 "†
7stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst	7stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
’
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
’
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
’
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst	;stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
’
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
’
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
’
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¿
 "¨
Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Hstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ø
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst	;stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ô
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¡
 "Š
9stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst	9stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ô
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¡
 "Š
9stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst	9stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ô
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¡
 "Š
9stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst	9stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ì
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2™
 "‚
5stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst	5stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ì
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2™
 "‚
5stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst	5stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ì
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2™
 "‚
5stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst	5stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
Œ
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
Œ
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
Œ
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ð
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2
 "†
7stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst	7stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
Œ
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
Œ
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
Œ
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
ð
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2
 "†
7stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst	7stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
Œ
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
Œ
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
Œ
ãenum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2¹
 "¢
Estat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst	Estat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E22default:default8ZAVAL-156h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
DRC AVAL-1562default:default2
1002default:defaultZ17-14h px 
à
›enum_AREG_0_connects_CEA1_GND_connects_CEA2_GND: %s: When DSP48E2 attribute AREG is set to 0, the CEA1 and CEA2 pins should be tied to GND to save power.%s*DRC2`
 "J
stat_regs_inst/i_DSP_cntr	stat_regs_inst/i_DSP_cntr2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1669h px 
à
›enum_AREG_0_connects_CEA1_GND_connects_CEA2_GND: %s: When DSP48E2 attribute AREG is set to 0, the CEA1 and CEA2 pins should be tied to GND to save power.%s*DRC2`
 "J
stat_regs_inst/i_DSP_rate	stat_regs_inst/i_DSP_rate2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1669h px 
º
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¾
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
º
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
º
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
º
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
º
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
º
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
º
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
¼
±enum_AREG_1_connects_CEA1_GND: %s: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1671h px 
Þ
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2!
DRC REQP-16712default:default2
1002default:defaultZ17-14h px 
à
›enum_BREG_0_connects_CEB1_GND_connects_CEB2_GND: %s: When DSP48E2 attribute BREG is set to 0, the CEB1 and CEB2 pins should be tied to GND to save power.%s*DRC2`
 "J
stat_regs_inst/i_DSP_cntr	stat_regs_inst/i_DSP_cntr2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1673h px 
à
›enum_BREG_0_connects_CEB1_GND_connects_CEB2_GND: %s: When DSP48E2 attribute BREG is set to 0, the CEB1 and CEB2 pins should be tied to GND to save power.%s*DRC2`
 "J
stat_regs_inst/i_DSP_rate	stat_regs_inst/i_DSP_rate2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1673h px 
º
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¾
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
º
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
º
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
º
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
º
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
º
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
º
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
¼
±enum_BREG_1_connects_CEB1_GND: %s: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1675h px 
Þ
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2!
DRC REQP-16752default:default2
1002default:defaultZ17-14h px 
†
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2™
 "‚
5g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst	5g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
†
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2™
 "‚
5g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst	5g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
†
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2™
 "‚
5g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst	5g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ý
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2
 "z
1g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst	1g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
†
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2™
 "‚
5g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst	5g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
†
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2™
 "‚
5g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst	5g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
†
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2™
 "‚
5g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst	5g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ý
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2
 "z
1g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst	1g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
†
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2™
 "‚
5g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst	5g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
†
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2™
 "‚
5g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst	5g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
†
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2™
 "‚
5g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst	5g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ý
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2
 "z
1g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst	1g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst	6g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst	6g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ˆ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2›
 "„
6g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst	6g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
ÿ
‡enum_CREG_0_connects_CEC_GND: %s: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.%s*DRC2’
 "|
2g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst	2g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1678h px 
Þ
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2!
DRC REQP-16782default:default2
1002default:defaultZ17-14h px 

‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
”
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2§
 "
<stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2	<stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 

‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 

‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 

‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 

‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 

‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 

‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2£
 "Œ
:stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2	:stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
’
‡enum_PREG_0_connects_CEP_GND: %s: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.%s*DRC2¥
 "Ž
;stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2	;stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst22default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1680h px 
Þ
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2!
DRC REQP-16802default:default2
1002default:defaultZ17-14h px 
ˆ
‹with_OPMODE_USE_MULT_NONE: %s: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.%s*DRC2—
 "€
4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[0].DSP48E2_inst	4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[0].DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1681h px 
Š
‹with_OPMODE_USE_MULT_NONE: %s: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.%s*DRC2™
 "‚
5stat_regs_inst/i_cntr_rst_ctrl/g_DSP[10].DSP48E2_inst	5stat_regs_inst/i_cntr_rst_ctrl/g_DSP[10].DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1681h px 
ˆ
‹with_OPMODE_USE_MULT_NONE: %s: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.%s*DRC2—
 "€
4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst	4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1681h px 
ˆ
‹with_OPMODE_USE_MULT_NONE: %s: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.%s*DRC2—
 "€
4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[2].DSP48E2_inst	4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[2].DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1681h px 
ˆ
‹with_OPMODE_USE_MULT_NONE: %s: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.%s*DRC2—
 "€
4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[3].DSP48E2_inst	4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[3].DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1681h px 
ˆ
‹with_OPMODE_USE_MULT_NONE: %s: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.%s*DRC2—
 "€
4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[4].DSP48E2_inst	4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[4].DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1681h px 
ˆ
‹with_OPMODE_USE_MULT_NONE: %s: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.%s*DRC2—
 "€
4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[5].DSP48E2_inst	4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[5].DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1681h px 
ˆ
‹with_OPMODE_USE_MULT_NONE: %s: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.%s*DRC2—
 "€
4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[6].DSP48E2_inst	4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[6].DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1681h px 
ˆ
‹with_OPMODE_USE_MULT_NONE: %s: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.%s*DRC2—
 "€
4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[7].DSP48E2_inst	4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[7].DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1681h px 
ˆ
‹with_OPMODE_USE_MULT_NONE: %s: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.%s*DRC2—
 "€
4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[8].DSP48E2_inst	4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[8].DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1681h px 
ˆ
‹with_OPMODE_USE_MULT_NONE: %s: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.%s*DRC2—
 "€
4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[9].DSP48E2_inst	4stat_regs_inst/i_cntr_rst_ctrl/g_DSP[9].DSP48E2_inst2default:default2default:default2A
 )DRC|Netlist|Instance|Required Pin|DSP48E22default:default8Z	REQP-1681h px 
Ë
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2û
 "ä
fSFP_GEN[0].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	fSFP_GEN[0].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[0].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[0].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[0].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[0].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[0].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[0].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[0].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[0].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ë
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2û
 "ä
fSFP_GEN[0].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	fSFP_GEN[0].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ë
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2û
 "ä
fSFP_GEN[0].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	fSFP_GEN[0].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ë
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2û
 "ä
fSFP_GEN[0].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	fSFP_GEN[0].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ë
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2û
 "ä
fSFP_GEN[0].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	fSFP_GEN[0].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ë
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2û
 "ä
fSFP_GEN[0].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	fSFP_GEN[0].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ë
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2û
 "ä
fSFP_GEN[0].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	fSFP_GEN[0].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ë
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2û
 "ä
fSFP_GEN[0].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	fSFP_GEN[0].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ë
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2û
 "ä
fSFP_GEN[0].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	fSFP_GEN[0].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ë
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2û
 "ä
fSFP_GEN[0].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	fSFP_GEN[0].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[10].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[10].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[10].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[10].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[10].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[10].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[10].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[10].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
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éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[10].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[10].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[10].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[10].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[10].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[10].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[10].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[10].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[10].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[10].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[10].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[10].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[10].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[10].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[10].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[10].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[10].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[10].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[10].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[10].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[11].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[11].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[11].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[11].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[11].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[11].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[11].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[11].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[11].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[11].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[11].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[11].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[11].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[11].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[11].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[11].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[11].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[11].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[11].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[11].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[11].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[11].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[11].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[11].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[11].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[11].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[11].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[11].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[12].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[12].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[12].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[12].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[12].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[12].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[12].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[12].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[12].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[12].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[12].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[12].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[12].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[12].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[12].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[12].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[12].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[12].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[12].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[12].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[12].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[12].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[12].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[12].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[12].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[12].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[12].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[12].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[13].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[13].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[13].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[13].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[13].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[13].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[13].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[13].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[13].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[13].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[13].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[13].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[13].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[13].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[13].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[13].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[13].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[13].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[13].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[13].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[13].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[13].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[13].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[13].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[13].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[13].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[14].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[14].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[14].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[14].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[14].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[14].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[14].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[14].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[14].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[14].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[14].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[14].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[14].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[14].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[14].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[14].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[14].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[14].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[14].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[14].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[14].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[14].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[14].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[14].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[14].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[14].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[14].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[14].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[15].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[15].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[15].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[15].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[15].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[15].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
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éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[15].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[15].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Ï
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
 "è
hSFP_GEN[15].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[15].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[15].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[15].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[15].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[15].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[15].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[15].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[15].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[15].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[15].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[15].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[15].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[15].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[15].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[15].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[15].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[15].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[15].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[15].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
Í
éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ý
 "æ
gSFP_GEN[16].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	gSFP_GEN[16].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E22default:default8Z	REQP-1934h px 
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éRAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (%s) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2ÿ
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hSFP_GEN[16].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg	hSFP_GEN[16].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2default:default2B
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14*common2!
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1002default:defaultZ17-14h px 
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DRC finished with %s
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End Record