*** Running vivado with args -log ngFEC_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source ngFEC_top.tcl -notrace ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source ngFEC_top.tcl -notrace Command: link_design -top ngFEC_top -part xcku115-flva2104-1-c Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xcku115-flva2104-1-c INFO: [Project 1-454] Reading design checkpoint 'd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip.dcp' for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' INFO: [Project 1-454] Reading design checkpoint 'd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0.dcp' for cell 'i_axi_slave/i_aurora' INFO: [Project 1-454] Reading design checkpoint 'd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B.dcp' for cell 'i_axi_slave/i_axi_chip2chip' INFO: [Project 1-454] Reading design checkpoint 'd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/ttc_mgt.dcp' for cell 'i_tcds2_if/i_mgt_wrapper/i_mgt' Netlist sorting complete. Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 3330.289 ; gain = 126.449 INFO: [Netlist 29-17] Analyzing 10914 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 15 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B.xdc] for cell 'i_axi_slave/i_axi_chip2chip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B.xdc] for cell 'i_axi_slave/i_axi_chip2chip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/synth/ttc_mgt.xdc] for cell 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/synth/ttc_mgt.xdc] for cell 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/ip_1/aurora_64b66b_0_fifo_gen_master.xdc] for cell 'i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/ip_1/aurora_64b66b_0_fifo_gen_master.xdc] for cell 'i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/ip_0/synth/aurora_64b66b_0_gt.xdc] for cell 'i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/ip_0/synth/aurora_64b66b_0_gt.xdc] for cell 'i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0.xdc] for cell 'i_axi_slave/i_aurora/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0.xdc] for cell 'i_axi_slave/i_aurora/inst' Parsing XDC File [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc] INFO: [Timing 38-35] Done setting XDC timing constraints. [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:126] WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:126] INFO: [Timing 38-2] Deriving generated clocks [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc:126] get_clocks: Time (s): cpu = 00:02:57 ; elapsed = 00:01:42 . Memory (MB): peak = 6324.652 ; gain = 1849.250 Finished Parsing XDC File [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc] Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_clocks.xdc] for cell 'i_axi_slave/i_axi_chip2chip/inst' get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 6333.559 ; gain = 0.000 Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_clocks.xdc] for cell 'i_axi_slave/i_axi_chip2chip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/ip_1/aurora_64b66b_0_fifo_gen_master_clocks.xdc] for cell 'i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/ip_1/aurora_64b66b_0_fifo_gen_master_clocks.xdc] for cell 'i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0_clocks.xdc] for cell 'i_axi_slave/i_aurora/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0_clocks.xdc] for cell 'i_axi_slave/i_aurora/inst' INFO: [Project 1-1715] 6 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-441] Inserted BUFG_GT_SYNC i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC for BUFG_GT i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst INFO: [Opt 31-441] Inserted BUFG_GT_SYNC i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_1 for BUFG_GT i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.415 . Memory (MB): peak = 6333.559 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1045 instances were transformed. DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 1003 instances IBUF => IBUF (IBUFCTRL, INBUF): 16 instances IOBUF => IOBUF (IBUFCTRL, INBUF, OBUFT): 18 instances RAM64M8 => RAM64M8 (RAMD64E(x8)): 4 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 4 instances 16 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:08:19 ; elapsed = 00:06:50 . Memory (MB): peak = 6333.559 ; gain = 5305.758 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 6333.559 ; gain = 0.000 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks Ending Cache Timing Information Task | Checksum: 1061cdb86 Time (s): cpu = 00:02:46 ; elapsed = 00:01:37 . Memory (MB): peak = 6333.559 ; gain = 0.000 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 2152 inverter(s) to 175268 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 16d51a538 Time (s): cpu = 00:01:43 ; elapsed = 00:01:20 . Memory (MB): peak = 6481.855 ; gain = 148.297 INFO: [Opt 31-389] Phase Retarget created 672 cells and removed 5569 cells INFO: [Opt 31-1021] In phase Retarget, 775 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 9d27dc2f Time (s): cpu = 00:01:50 ; elapsed = 00:01:27 . Memory (MB): peak = 6481.855 ; gain = 148.297 INFO: [Opt 31-389] Phase Constant propagation created 2 cells and removed 150 cells INFO: [Opt 31-1021] In phase Constant propagation, 3 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Sweep Phase 3 Sweep | Checksum: 103f40dd1 Time (s): cpu = 00:02:18 ; elapsed = 00:01:55 . Memory (MB): peak = 6481.855 ; gain = 148.297 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 2121 cells INFO: [Opt 31-1021] In phase Sweep, 4118 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT. INFO: [Opt 31-129] Inserted BUFG to drive high-fanout reset|set|enable net. BUFG cell: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/sync_flop_2[1]_BUFG_inst, Net: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/sync_flop_2[1] Phase 4 BUFG optimization | Checksum: ad0cddfa Time (s): cpu = 00:02:51 ; elapsed = 00:02:28 . Memory (MB): peak = 6481.855 ; gain = 148.297 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells. INFO: [Opt 31-1021] In phase BUFG optimization, 6 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: ad0cddfa Time (s): cpu = 00:02:53 ; elapsed = 00:02:30 . Memory (MB): peak = 6481.855 ; gain = 148.297 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 1649b41fc Time (s): cpu = 00:02:58 ; elapsed = 00:02:35 . Memory (MB): peak = 6481.855 ; gain = 148.297 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 4 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 672 | 5569 | 775 | | Constant propagation | 2 | 150 | 3 | | Sweep | 0 | 2121 | 4118 | | BUFG optimization | 1 | 0 | 6 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 4 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 6481.855 ; gain = 0.000 Ending Logic Optimization Task | Checksum: 7649f3cf Time (s): cpu = 00:03:33 ; elapsed = 00:03:07 . Memory (MB): peak = 6481.855 ; gain = 148.297 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 2097 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 48 WE to EN ports Number of BRAM Ports augmented: 1 newly gated: 731 Total Ports: 4194 Ending PowerOpt Patch Enables Task | Checksum: 120eb38a4 Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 13867.949 ; gain = 0.000 Ending Power Optimization Task | Checksum: 120eb38a4 Time (s): cpu = 00:14:37 ; elapsed = 00:07:24 . Memory (MB): peak = 13867.949 ; gain = 7386.094 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 120eb38a4 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 13867.949 ; gain = 0.000 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.764 . Memory (MB): peak = 13867.949 ; gain = 0.000 Ending Netlist Obfuscation Task | Checksum: 1789d7492 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.764 . Memory (MB): peak = 13867.949 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 46 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:21:17 ; elapsed = 00:12:23 . Memory (MB): peak = 13867.949 ; gain = 7534.391 INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.221 . Memory (MB): peak = 13867.949 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/impl_1/ngFEC_top_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:06:52 ; elapsed = 00:03:55 . Memory (MB): peak = 13867.949 ; gain = 0.000 INFO: [runtcl-4] Executing : report_drc -file ngFEC_top_drc_opted.rpt -pb ngFEC_top_drc_opted.pb -rpx ngFEC_top_drc_opted.rpx Command: report_drc -file ngFEC_top_drc_opted.rpt -pb ngFEC_top_drc_opted.pb -rpx ngFEC_top_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/impl_1/ngFEC_top_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:04:42 ; elapsed = 00:02:30 . Memory (MB): peak = 13867.949 ; gain = 0.000 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.420 . Memory (MB): peak = 13867.949 ; gain = 0.000 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 90841470 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.724 . Memory (MB): peak = 13867.949 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.427 . Memory (MB): peak = 13867.949 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 170987bc2 Time (s): cpu = 00:02:02 ; elapsed = 00:01:31 . Memory (MB): peak = 13867.949 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1f41bb22d Time (s): cpu = 00:09:16 ; elapsed = 00:06:22 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1f41bb22d Time (s): cpu = 00:09:18 ; elapsed = 00:06:24 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 1 Placer Initialization | Checksum: 1f41bb22d Time (s): cpu = 00:09:24 ; elapsed = 00:06:31 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 182a4d8c3 Time (s): cpu = 00:11:55 ; elapsed = 00:08:08 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1971af5e3 Time (s): cpu = 00:13:18 ; elapsed = 00:08:58 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 2.3 Global Placement Core SLR(matching) [0-1] 12 11 15 81 522 1440 1049 83 52 16 7 0 Total: 3288 SLR(matching) [0-1] 20 13 29 30 984 895 1014 267 12 10 4 10 Total: 3288 SLR(matching) [0-1] 14 22 14 21 966 937 1113 174 6 6 10 5 Total: 3288 SLR(matching) [0-1] 11 22 19 20 820 1062 1245 58 8 9 5 9 Total: 3288 SLR(matching) [0-1] 11 22 19 19 792 1116 1227 51 8 9 5 9 Total: 3288 SLR(matching) [0-1] 12 21 19 19 753 1142 1244 47 8 7 6 10 Total: 3288 SLR(matching) [0-1] 13 18 18 11 722 1190 1246 41 8 4 11 6 Total: 3288 SLR(matching) [0-1] 9 18 18 14 716 1204 1240 38 8 8 6 9 Total: 3288 SLR(matching) [0-1] 14 17 12 15 702 1197 1265 40 7 4 9 6 Total: 3288 SLR(matching) [0-1] 13 20 14 19 683 1162 1309 46 8 5 4 5 Total: 3288 SLR(matching) [0-1] 12 21 19 16 686 1114 1339 50 8 8 6 9 Total: 3288 SLR(matching) [0-1] 13 20 14 14 684 1086 1382 44 8 8 9 6 Total: 3288 SLR(matching) [0-1] 12 21 18 17 792 960 1388 49 8 8 6 9 Total: 3288 SLR(matching) [0-1] 20 13 22 64 881 850 1285 125 6 10 12 0 Total: 3288 SLR(matching) [0-1] 15 25 21 94 816 836 1040 387 38 8 6 2 Total: 3288 SLR(matching) [0-1] 20 34 66 164 827 746 888 445 77 4 11 6 Total: 3288 SLR(matching) [0-1] 28 25 141 123 741 820 836 352 181 28 7 6 Total: 3288 SLR(matching) [0-1] 45 29 139 137 735 801 797 294 252 38 18 3 Total: 3288 SLR(matching) [0-1] 44 17 144 136 736 776 811 298 228 62 30 6 Total: 3288 SLR(matching) [0-1] 44 17 128 145 747 736 820 293 244 66 41 7 Total: 3288 SLR(matching) [0-1] 47 44 108 173 800 657 843 313 187 56 56 4 Total: 3288 SLR(matching) [0-1] 47 46 113 217 782 632 806 294 237 55 48 11 Total: 3288 SLR(matching) [0-1] 50 57 116 232 797 575 812 284 239 60 52 14 Total: 3288 SLR(matching) [0-1] 62 40 114 236 828 571 789 294 235 60 47 12 Total: 3288 SLR(matching) [0-1] 68 52 89 235 813 562 788 324 228 63 52 14 Total: 3288 SLR(matching) [0-1] 70 51 92 235 821 582 772 303 233 67 48 14 Total: 3288 SLR(matching) [0-1] 72 44 97 224 815 607 749 289 254 80 45 12 Total: 3288 SLR(matching) [0-1] 74 49 94 254 811 592 751 299 221 84 47 12 Total: 3288 SLR(matching) [0-1] 76 44 110 244 814 588 761 272 238 80 49 12 Total: 3288 SLR(matching) [0-1] 75 50 96 242 832 583 750 307 212 82 44 15 Total: 3288 SLR(matching) [0-1] 81 45 101 240 815 591 753 308 211 82 47 14 Total: 3288 SLR(matching) [0-1] 76 47 101 245 827 580 750 293 213 93 47 16 Total: 3288 SLR(matching) [0-1] 84 43 100 253 830 570 748 286 214 100 48 12 Total: 3288 SLR(matching) [0-1] 85 51 94 257 813 576 749 280 235 86 49 13 Total: 3288 SLR(matching) [0-1] 81 48 98 257 827 571 756 264 233 87 53 13 Total: 3288 SLR(matching) [0-1] 78 47 94 246 828 582 761 289 192 105 52 14 Total: 3288 SLR(matching) [0-1] 76 49 92 252 822 589 761 277 210 102 44 14 Total: 3288 SLR(matching) [0-1] 78 47 104 235 837 572 766 263 227 101 45 13 Total: 3288 SLR(matching) [0-1] 76 44 99 249 826 576 764 277 213 109 41 14 Total: 3288 SLR(matching) [0-1] 81 46 103 243 820 575 765 288 211 96 48 12 Total: 3288 SLR(matching) [0-1] 78 49 97 246 828 564 773 281 222 87 50 13 Total: 3288 SLR(matching) [0-1] 76 50 92 265 813 578 759 282 222 89 49 13 Total: 3288 Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 8 LUTNM shape to break, 14469 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 6, two critical 2, total 8, new lutff created 0 INFO: [Physopt 32-775] End 1 Pass. Optimized 6317 nets or cells. Created 8 new cells, deleted 6309 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 10 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net i_AXI4_to_ipbus/Q[8]. Replicated 12 times. INFO: [Physopt 32-81] Processed net i_AXI4_to_ipbus/Q[12]. Replicated 15 times. INFO: [Physopt 32-81] Processed net i_AXI4_to_ipbus/Q[9]. Replicated 7 times. INFO: [Physopt 32-81] Processed net i_AXI4_to_ipbus/ipb_mosi[0][ipb_addr][18]. Replicated 12 times. INFO: [Physopt 32-81] Processed net i_AXI4_to_ipbus/Q[13]. Replicated 15 times. INFO: [Physopt 32-81] Processed net i_AXI4_to_ipbus/Q[10]. Replicated 7 times. INFO: [Physopt 32-81] Processed net i_AXI4_to_ipbus/ipb_mosi[0][ipb_addr][11]. Replicated 20 times. INFO: [Physopt 32-81] Processed net i_AXI4_to_ipbus/ipb_mosi[0][ipb_addr][19]. Replicated 13 times. INFO: [Physopt 32-81] Processed net i_AXI4_to_ipbus/ipb_mosi[0][ipb_addr][26]. Replicated 12 times. INFO: [Physopt 32-81] Processed net TX_CLKEN. Replicated 68 times. INFO: [Physopt 32-232] Optimized 10 nets. Created 181 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 10 nets or cells. Created 181 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 13929.094 ; gain = 0.000 INFO: [Physopt 32-76] Pass 1. Identified 1 candidate net for fanout optimization. INFO: [Physopt 32-81] Processed net stat_regs_inst/wea. Replicated 9 times. INFO: [Physopt 32-232] Optimized 1 net. Created 9 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 9 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.659 . Memory (MB): peak = 13929.094 ; gain = 0.000 INFO: [Physopt 32-117] Net SFP_GEN[45].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 could not be optimized because driver SFP_GEN[45].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2 could not be replicated INFO: [Physopt 32-117] Net SFP_GEN[45].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 could not be optimized because driver SFP_GEN[45].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2 could not be replicated INFO: [Physopt 32-117] Net SFP_GEN[45].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 could not be optimized because driver SFP_GEN[45].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2 could not be replicated INFO: [Physopt 32-68] No nets found for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.406 . Memory (MB): peak = 13929.094 ; gain = 0.000 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 8 | 6309 | 6317 | 0 | 1 | 00:00:26 | | Very High Fanout | 181 | 0 | 10 | 0 | 1 | 00:00:37 | | Fanout | 9 | 0 | 1 | 0 | 1 | 00:00:02 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 198 | 6309 | 6328 | 0 | 10 | 00:01:08 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 1a23a745e Time (s): cpu = 00:40:21 ; elapsed = 00:28:03 . Memory (MB): peak = 13929.094 ; gain = 61.145 SLR(matching) [0-1] 114 44 101 304 821 633 737 253 176 76 28 11 Total: 3298 Phase 2.3 Global Placement Core | Checksum: 1f212ae24 Time (s): cpu = 00:41:39 ; elapsed = 00:29:04 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 2 Global Placement | Checksum: 1f212ae24 Time (s): cpu = 00:41:41 ; elapsed = 00:29:06 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 2a565b8bf Time (s): cpu = 00:43:54 ; elapsed = 00:30:32 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 3.2 Commit Most Macros & LUTRAMs SLR(matching) [0-1] 112 50 120 274 813 637 737 255 187 72 30 11 Total: 3298 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1fecabe16 Time (s): cpu = 00:46:58 ; elapsed = 00:32:42 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 3.3 Small Shape DP Phase 3.3.1 Small Shape Clustering SLR(matching) [0-1] 110 47 113 292 823 588 800 310 269 73 53 10 Total: 3488 Phase 3.3.1 Small Shape Clustering | Checksum: 24a823f0b Time (s): cpu = 00:55:00 ; elapsed = 00:38:18 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 3.3.2 DP Optimization SLR(matching) [0-1] 111 49 100 299 838 566 803 309 273 76 52 12 Total: 3488 SLR(matching) [0-1] 111 49 99 299 838 567 805 307 273 76 52 12 Total: 3488 SLR(matching) [0-1] 84 45 105 259 823 516 840 334 309 93 67 13 Total: 3488 SLR(matching) [0-1] 76 42 101 265 832 508 834 338 321 102 58 11 Total: 3488 SLR(matching) [0-1] 71 48 108 261 817 517 831 336 318 93 77 11 Total: 3488 SLR(matching) [0-1] 79 48 93 262 828 520 839 346 307 89 67 10 Total: 3488 SLR(matching) [0-1] 79 46 101 260 817 509 824 355 313 95 80 9 Total: 3488 SLR(matching) [0-1] 80 48 104 259 820 509 830 354 316 94 65 9 Total: 3488 SLR(matching) [0-1] 80 45 104 258 816 508 819 362 313 94 80 9 Total: 3488 SLR(matching) [0-1] 80 47 103 257 815 515 827 356 319 93 67 9 Total: 3488 SLR(matching) [0-1] 80 45 105 260 817 518 813 363 313 94 71 9 Total: 3488 SLR(matching) [0-1] 78 45 102 262 815 517 813 368 312 92 75 9 Total: 3488 SLR(matching) [0-1] 81 49 106 258 808 518 816 363 317 92 71 9 Total: 3488 SLR(matching) [0-1] 80 46 107 258 812 519 805 375 313 91 73 9 Total: 3488 SLR(matching) [0-1] 80 47 106 265 810 517 802 374 310 93 75 9 Total: 3488 SLR(matching) [0-1] 80 46 107 267 807 515 801 377 309 93 76 10 Total: 3488 SLR(matching) [0-1] 83 48 107 266 807 515 813 364 314 95 66 10 Total: 3488 SLR(matching) [0-1] 82 45 107 268 804 523 797 374 319 86 73 10 Total: 3488 SLR(matching) [0-1] 81 45 104 263 810 529 799 373 316 87 70 11 Total: 3488 SLR(matching) [0-1] 84 48 102 265 803 529 811 368 316 85 66 11 Total: 3488 SLR(matching) [0-1] 82 46 103 262 808 535 802 369 316 84 70 11 Total: 3488 SLR(matching) [0-1] 81 47 101 263 808 540 797 371 315 83 70 12 Total: 3488 SLR(matching) [0-1] 83 49 102 268 799 536 811 362 316 85 65 12 Total: 3488 SLR(matching) [0-1] 83 47 101 265 805 539 806 363 311 85 72 11 Total: 3488 SLR(matching) [0-1] 83 47 99 264 804 543 809 356 313 86 73 11 Total: 3488 SLR(matching) [0-1] 79 56 96 249 819 548 816 358 310 81 64 12 Total: 3488 SLR(matching) [0-1] 71 48 102 264 833 536 811 353 309 80 68 13 Total: 3488 SLR(matching) [0-1] 79 46 115 263 807 545 814 350 308 85 65 11 Total: 3488 SLR(matching) [0-1] 81 50 105 264 811 529 817 355 314 85 66 11 Total: 3488 SLR(matching) [0-1] 70 53 102 267 819 534 814 348 318 84 66 13 Total: 3488 SLR(matching) [0-1] 81 49 103 265 812 534 815 351 310 88 69 11 Total: 3488 SLR(matching) [0-1] 81 51 102 266 811 535 812 351 312 87 69 11 Total: 3488 SLR(matching) [0-1] 71 55 99 272 815 541 812 343 318 86 63 13 Total: 3488 SLR(matching) [0-1] 83 48 103 259 821 545 813 348 312 79 65 12 Total: 3488 SLR(matching) [0-1] 77 61 91 258 827 547 808 345 314 82 65 13 Total: 3488 Phase 3.3.2 DP Optimization | Checksum: 2580128e1 Time (s): cpu = 01:27:18 ; elapsed = 01:01:07 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 3.3.3 Flow Legalize Slice Clusters Phase 3.3.3 Flow Legalize Slice Clusters | Checksum: 1e268081c Time (s): cpu = 01:27:28 ; elapsed = 01:01:14 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 3.3.4 Slice Area Swap SLR(matching) [0-1] 111 50 105 299 833 574 798 306 271 77 52 12 Total: 3488 SLR(matching) [0-1] 111 50 118 286 833 588 812 311 267 75 56 12 Total: 3519 Phase 3.3.4 Slice Area Swap | Checksum: 1fbe610c9 Time (s): cpu = 01:32:10 ; elapsed = 01:04:16 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 3.3 Small Shape DP | Checksum: 295d3e3fb Time (s): cpu = 01:36:09 ; elapsed = 01:06:25 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 3.4 Re-assign LUT pins Phase 3.4 Re-assign LUT pins | Checksum: 1d166b82c Time (s): cpu = 01:37:10 ; elapsed = 01:07:41 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 3.5 Pipeline Register Optimization Phase 3.5 Pipeline Register Optimization | Checksum: 2a729f503 Time (s): cpu = 01:37:26 ; elapsed = 01:07:58 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 3.6 Fast Optimization Phase 3.6 Fast Optimization | Checksum: 297a08900 Time (s): cpu = 02:02:47 ; elapsed = 01:27:23 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 3 Detail Placement | Checksum: 297a08900 Time (s): cpu = 02:02:52 ; elapsed = 01:27:28 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1bf81c123 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.126 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1a38a7008 Time (s): cpu = 00:01:19 ; elapsed = 00:00:43 . Memory (MB): peak = 13929.094 ; gain = 0.000 INFO: [Place 46-35] Processed net fabric_clk_div2, inserted BUFG to drive 5252 loads. INFO: [Place 46-45] Replicated bufg driver fabric_clk_div2_reg_replica INFO: [Place 46-35] Processed net SFP_GEN[5].ngCCM_gbt/fabric_clk_div2_reg[0], inserted BUFG to drive 1392 loads. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 2, Replicated BUFG Driver: 1, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 18f9d080b Time (s): cpu = 00:02:12 ; elapsed = 00:01:15 . Memory (MB): peak = 13929.094 ; gain = 0.000 Phase 4.1.1.1 BUFG Insertion | Checksum: 14de17a80 Time (s): cpu = 02:25:03 ; elapsed = 01:43:41 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 4.1.1.2 BUFG Replication INFO: [Place 46-68] Processed net fabric_clk_div2, BUFG replication was skipped in SLR 0 as timing constraints are met. INFO: [Place 46-63] BUFG replication identified 1 candidate nets: Replicated nets: 0, Replicated BUFGs: 0, Replicated BUFG Driver: 0, Skipped due to Placement / Routing Conflict: 0, Skipped due to Timing: 1, Skipped due to constraints: 0 Phase 4.1.1.2 BUFG Replication | Checksum: 14de17a80 Time (s): cpu = 02:25:18 ; elapsed = 01:43:54 . Memory (MB): peak = 13929.094 ; gain = 61.145 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.400. For the most accurate timing information please run report_timing. Phase 4.1.1.3 Replication INFO: [Place 46-19] Post Replication Timing Summary WNS=0.400. For the most accurate timing information please run report_timing. Phase 4.1.1.3 Replication | Checksum: 1e10a5bb4 Time (s): cpu = 02:30:46 ; elapsed = 01:47:36 . Memory (MB): peak = 13929.094 ; gain = 61.145 Time (s): cpu = 02:30:46 ; elapsed = 01:47:36 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 4.1 Post Commit Optimization | Checksum: 1e10a5bb4 Time (s): cpu = 02:30:51 ; elapsed = 01:47:42 . Memory (MB): peak = 13929.094 ; gain = 61.145 Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 13929.094 ; gain = 0.000 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1fd33e372 Time (s): cpu = 02:31:16 ; elapsed = 01:48:05 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 16x16| 8x8| |___________|___________________|___________________| | South| 8x8| 8x8| |___________|___________________|___________________| | East| 1x1| 4x4| |___________|___________________|___________________| | West| 1x1| 8x8| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1fd33e372 Time (s): cpu = 02:31:22 ; elapsed = 01:48:12 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 4.3 Placer Reporting | Checksum: 1fd33e372 Time (s): cpu = 02:31:28 ; elapsed = 01:48:17 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.437 . Memory (MB): peak = 13929.094 ; gain = 0.000 Time (s): cpu = 02:31:29 ; elapsed = 01:48:18 . Memory (MB): peak = 13929.094 ; gain = 61.145 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 218da79b8 Time (s): cpu = 02:31:34 ; elapsed = 01:48:23 . Memory (MB): peak = 13929.094 ; gain = 61.145 Ending Placer Task | Checksum: 1430d30c8 Time (s): cpu = 02:31:34 ; elapsed = 01:48:23 . Memory (MB): peak = 13929.094 ; gain = 61.145 INFO: [Common 17-83] Releasing license: Implementation 113 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 02:32:23 ; elapsed = 01:48:57 . Memory (MB): peak = 13929.094 ; gain = 61.145 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:02:50 ; elapsed = 00:00:54 . Memory (MB): peak = 13929.094 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/impl_1/ngFEC_top_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:05:06 ; elapsed = 00:02:28 . Memory (MB): peak = 13929.094 ; gain = 0.000 INFO: [runtcl-4] Executing : report_io -file ngFEC_top_io_placed.rpt report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.508 . Memory (MB): peak = 13929.094 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file ngFEC_top_utilization_placed.rpt -pb ngFEC_top_utilization_placed.pb report_utilization: Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 13929.094 ; gain = 0.000 INFO: [runtcl-4] Executing : report_control_sets -verbose -file ngFEC_top_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 13929.094 ; gain = 0.000 Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 123 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:16:23 ; elapsed = 00:11:12 . Memory (MB): peak = 13929.094 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:02:46 ; elapsed = 00:00:53 . Memory (MB): peak = 13929.094 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/impl_1/ngFEC_top_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:05:05 ; elapsed = 00:02:29 . Memory (MB): peak = 13929.094 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs Checksum: PlaceDB: 5ead01ff ConstDB: 0 ShapeSum: c836a70b RouteDB: 1c2987be Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 8ab4bb84 Time (s): cpu = 00:05:04 ; elapsed = 00:03:57 . Memory (MB): peak = 13929.094 ; gain = 0.000 Post Restoration Checksum: NetGraph: f9cea8c3 NumContArr: de3110f2 Constraints: df07a102 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 2b7075ab7 Time (s): cpu = 00:05:19 ; elapsed = 00:04:13 . Memory (MB): peak = 13929.094 ; gain = 0.000 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 2b7075ab7 Time (s): cpu = 00:05:23 ; elapsed = 00:04:17 . Memory (MB): peak = 13929.094 ; gain = 0.000 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 2b7075ab7 Time (s): cpu = 00:05:25 ; elapsed = 00:04:19 . Memory (MB): peak = 13929.094 ; gain = 0.000 Phase 2.4 Global Clock Net Routing Number of Nodes with overlaps = 0 Phase 2.4 Global Clock Net Routing | Checksum: 16b506866 Time (s): cpu = 00:06:22 ; elapsed = 00:05:05 . Memory (MB): peak = 13929.094 ; gain = 0.000 Phase 2.5 Update Timing Phase 2.5 Update Timing | Checksum: 2a438a02a Time (s): cpu = 00:17:17 ; elapsed = 00:11:47 . Memory (MB): peak = 13929.094 ; gain = 0.000 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.457 | TNS=0.000 | WHS=-0.509 | THS=-2640.571| Phase 2.6 Update Timing for Bus Skew Phase 2.6.1 Update Timing Phase 2.6.1 Update Timing | Checksum: 2f7b1671b Time (s): cpu = 00:53:48 ; elapsed = 00:41:01 . Memory (MB): peak = 15680.699 ; gain = 1751.605 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.457 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.6 Update Timing for Bus Skew | Checksum: 2c50ed7a8 Time (s): cpu = 00:53:51 ; elapsed = 00:41:04 . Memory (MB): peak = 15680.699 ; gain = 1751.605 Phase 2 Router Initialization | Checksum: 2fd51d4b6 Time (s): cpu = 00:53:56 ; elapsed = 00:41:08 . Memory (MB): peak = 15680.699 ; gain = 1751.605 Router Utilization Summary Global Vertical Routing Utilization = 5.20412e-05 % Global Horizontal Routing Utilization = 0.000271223 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 830201 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 667860 Number of Partially Routed Nets = 162341 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 2fd51d4b6 Time (s): cpu = 00:54:27 ; elapsed = 00:41:28 . Memory (MB): peak = 15680.699 ; gain = 1751.605 Phase 3 Initial Routing | Checksum: 21517f610 Time (s): cpu = 01:00:01 ; elapsed = 00:45:04 . Memory (MB): peak = 15680.699 ; gain = 1751.605 INFO: [Route 35-449] Initial Estimated Congestion ________________________________________________________________________ | | Global Congestion | Long Congestion | Short Congestion | | |___________________|___________________|___________________| | Direction | Size | % Tiles | Size | % Tiles | Size | % Tiles | |___________|________|__________|________|__________|________|__________| | NORTH| 4x4| 0.25| 8x8| 0.77| 4x4| 0.73| |___________|________|__________|________|__________|________|__________| | SOUTH| 8x8| 0.65| 16x16| 1.75| 8x8| 0.75| |___________|________|__________|________|__________|________|__________| | EAST| 2x2| 0.03| 2x2| 0.33| 2x2| 0.43| |___________|________|__________|________|__________|________|__________| | WEST| 2x2| 0.04| 4x4| 0.26| 8x8| 0.76| |___________|________|__________|________|__________|________|__________| Congestion Report LONG Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): SOUTH INT_X40Y424->INT_X47Y447 (CLE_M_X40Y424->DSP_X47Y445) INT_X40Y432->INT_X47Y439 (CLE_M_X40Y432->DSP_X47Y435) INT_X40Y384->INT_X47Y391 (CLE_M_X40Y384->DSP_X47Y390) INT_X40Y376->INT_X47Y383 (CLE_M_X40Y376->DSP_X47Y380) Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 157411 Number of Nodes with overlaps = 11581 Number of Nodes with overlaps = 1416 Number of Nodes with overlaps = 297 Number of Nodes with overlaps = 84 Number of Nodes with overlaps = 39 Number of Nodes with overlaps = 30 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 21 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y4/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y14/NORTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y15/NORTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y5/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y6/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y7/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y12/NORTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y13/NORTHREFCLK0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.147 | TNS=0.000 | WHS=-0.112 | THS=-2.407 | Phase 4.1 Global Iteration 0 | Checksum: 2685081d1 Time (s): cpu = 02:08:07 ; elapsed = 01:39:03 . Memory (MB): peak = 16582.875 ; gain = 2653.781 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.147 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 20df39114 Time (s): cpu = 02:10:24 ; elapsed = 01:40:40 . Memory (MB): peak = 16582.875 ; gain = 2653.781 Phase 4 Rip-up And Reroute | Checksum: 20df39114 Time (s): cpu = 02:10:27 ; elapsed = 01:40:43 . Memory (MB): peak = 16582.875 ; gain = 2653.781 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 29374bc05 Time (s): cpu = 02:19:41 ; elapsed = 01:47:58 . Memory (MB): peak = 16582.875 ; gain = 2653.781 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.154 | TNS=0.000 | WHS=0.026 | THS=0.000 | Phase 5.1 Delay CleanUp | Checksum: 2ac7b76a5 Time (s): cpu = 02:19:47 ; elapsed = 01:48:04 . Memory (MB): peak = 16582.875 ; gain = 2653.781 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 2ac7b76a5 Time (s): cpu = 02:19:50 ; elapsed = 01:48:07 . Memory (MB): peak = 16582.875 ; gain = 2653.781 Phase 5 Delay and Skew Optimization | Checksum: 2ac7b76a5 Time (s): cpu = 02:19:53 ; elapsed = 01:48:10 . Memory (MB): peak = 16582.875 ; gain = 2653.781 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1e9fa3635 Time (s): cpu = 02:28:54 ; elapsed = 01:55:04 . Memory (MB): peak = 16582.875 ; gain = 2653.781 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.154 | TNS=0.000 | WHS=0.026 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 2f7e7a0f3 Time (s): cpu = 02:29:03 ; elapsed = 01:55:12 . Memory (MB): peak = 16582.875 ; gain = 2653.781 Phase 6 Post Hold Fix | Checksum: 2f7e7a0f3 Time (s): cpu = 02:29:06 ; elapsed = 01:55:15 . Memory (MB): peak = 16582.875 ; gain = 2653.781 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 15.9176 % Global Horizontal Routing Utilization = 15.9654 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 270312e0b Time (s): cpu = 02:29:44 ; elapsed = 01:55:46 . Memory (MB): peak = 16582.875 ; gain = 2653.781 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 270312e0b Time (s): cpu = 02:29:48 ; elapsed = 01:55:50 . Memory (MB): peak = 16582.875 ; gain = 2653.781 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y8/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y18/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y19/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y9/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y10/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y11/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y12/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y13/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y14/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y15/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y16/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y17/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y28/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y38/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y39/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y29/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y30/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y31/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y32/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y33/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y34/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y35/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y36/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y37/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y28/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y38/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y39/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y29/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y30/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y31/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y32/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y33/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y34/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y35/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y36/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y37/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin i_tcds2_if/i_mgt_wrapper/i_rxrecclk/I to physical pin GTHE3_COMMON_X1Y0/RXRECCLK3 Phase 9 Depositing Routes | Checksum: 270312e0b Time (s): cpu = 02:31:15 ; elapsed = 01:57:26 . Memory (MB): peak = 16582.875 ; gain = 2653.781 Common: SLR0 Initial Estimated Congestion ________________________________________________________________________ | | Global Congestion | Long Congestion | Short Congestion | | |___________________|___________________|___________________| | Direction | Size | % Tiles | Size | % Tiles | Size | % Tiles | |___________|________|__________|________|__________|________|__________| | NORTH| 2x2| 0.01| 2x2| 0.09| 4x4| 0.31| |___________|________|__________|________|__________|________|__________| | SOUTH| 2x2| 0.12| 8x8| 0.66| 4x4| 0.29| |___________|________|__________|________|__________|________|__________| | EAST| 1x1| 0.00| 2x2| 0.11| 2x2| 0.24| |___________|________|__________|________|__________|________|__________| | WEST| 1x1| 0.00| 2x2| 0.09| 4x4| 0.34| |___________|________|__________|________|__________|________|__________| SLR1 Initial Estimated Congestion ________________________________________________________________________ | | Global Congestion | Long Congestion | Short Congestion | | |___________________|___________________|___________________| | Direction | Size | % Tiles | Size | % Tiles | Size | % Tiles | |___________|________|__________|________|__________|________|__________| | NORTH| 4x4| 0.56| 8x8| 1.45| 4x4| 1.23| |___________|________|__________|________|__________|________|__________| | SOUTH| 8x8| 1.32| 16x16| 2.83| 8x8| 1.32| |___________|________|__________|________|__________|________|__________| | EAST| 2x2| 0.10| 2x2| 0.73| 4x4| 0.74| |___________|________|__________|________|__________|________|__________| | WEST| 2x2| 0.16| 4x4| 0.59| 8x8| 1.36| |___________|________|__________|________|__________|________|__________| Phase 10 Post Router Timing Phase 10.1 Update Timing Phase 10.1 Update Timing | Checksum: 196e67f3a Time (s): cpu = 02:37:36 ; elapsed = 02:01:55 . Memory (MB): peak = 16582.875 ; gain = 2653.781 INFO: [Route 35-57] Estimated Timing Summary | WNS=0.154 | TNS=0.000 | WHS=0.029 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 196e67f3a Time (s): cpu = 02:37:39 ; elapsed = 02:01:58 . Memory (MB): peak = 16582.875 ; gain = 2653.781 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 02:37:41 ; elapsed = 02:02:00 . Memory (MB): peak = 16582.875 ; gain = 2653.781 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 187 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 02:44:49 ; elapsed = 02:07:01 . Memory (MB): peak = 16582.875 ; gain = 2653.781 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:03:58 ; elapsed = 00:01:17 . Memory (MB): peak = 16582.875 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/impl_1/ngFEC_top_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:05:39 ; elapsed = 00:02:37 . Memory (MB): peak = 16582.875 ; gain = 0.000 INFO: [runtcl-4] Executing : report_drc -file ngFEC_top_drc_routed.rpt -pb ngFEC_top_drc_routed.pb -rpx ngFEC_top_drc_routed.rpx Command: report_drc -file ngFEC_top_drc_routed.rpt -pb ngFEC_top_drc_routed.pb -rpx ngFEC_top_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/impl_1/ngFEC_top_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:24:05 ; elapsed = 00:17:41 . Memory (MB): peak = 16582.875 ; gain = 0.000 INFO: [runtcl-4] Executing : report_methodology -file ngFEC_top_methodology_drc_routed.rpt -pb ngFEC_top_methodology_drc_routed.pb -rpx ngFEC_top_methodology_drc_routed.rpx Command: report_methodology -file ngFEC_top_methodology_drc_routed.rpt -pb ngFEC_top_methodology_drc_routed.pb -rpx ngFEC_top_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/impl_1/ngFEC_top_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:07:37 ; elapsed = 00:04:24 . Memory (MB): peak = 16582.875 ; gain = 0.000 INFO: [runtcl-4] Executing : report_power -file ngFEC_top_power_routed.rpt -pb ngFEC_top_power_summary_routed.pb -rpx ngFEC_top_power_routed.rpx Command: report_power -file ngFEC_top_power_routed.rpt -pb ngFEC_top_power_summary_routed.pb -rpx ngFEC_top_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 199 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:08:56 ; elapsed = 00:05:05 . Memory (MB): peak = 16582.875 ; gain = 0.000 INFO: [runtcl-4] Executing : report_route_status -file ngFEC_top_route_status.rpt -pb ngFEC_top_route_status.pb report_route_status: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 16582.875 ; gain = 0.000 INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file ngFEC_top_timing_summary_routed.rpt -pb ngFEC_top_timing_summary_routed.pb -rpx ngFEC_top_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Temperature grade: C, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:53 ; elapsed = 00:00:40 . Memory (MB): peak = 16582.875 ; gain = 0.000 INFO: [runtcl-4] Executing : report_incremental_reuse -file ngFEC_top_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file ngFEC_top_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 16582.875 ; gain = 0.000 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file ngFEC_top_bus_skew_routed.rpt -pb ngFEC_top_bus_skew_routed.pb -rpx ngFEC_top_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Temperature grade: C, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. write_mem_info: Time (s): cpu = 00:06:23 ; elapsed = 00:06:23 . Memory (MB): peak = 16582.875 ; gain = 0.000 Command: write_bitstream -force ngFEC_top.bit Attempting to get a license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. INFO: [Common 17-14] Message 'DRC DPIP-2' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. INFO: [Common 17-14] Message 'DRC DPOP-3' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 INFO: [Common 17-14] Message 'DRC DPREG-7' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC IOBUSSLRC-1] IO Bus SLR Crossings: Bus port GBT_refclk1_n spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 3, 1. Bits placed in SLR 0: 2, 0. WARNING: [DRC IOBUSSLRC-1] IO Bus SLR Crossings: Bus port GBT_refclk1_p spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 3, 1. Bits placed in SLR 0: 2, 0. WARNING: [DRC IOBUSSLRC-1] IO Bus SLR Crossings: Bus port GBT_rxn spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. WARNING: [DRC IOBUSSLRC-1] IO Bus SLR Crossings: Bus port GBT_rxp spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. WARNING: [DRC IOBUSSLRC-1] IO Bus SLR Crossings: Bus port GBT_txn spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. WARNING: [DRC IOBUSSLRC-1] IO Bus SLR Crossings: Bus port GBT_txp spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. WARNING: [DRC RTSTAT-10] No routable loads: 1 net(s) have no routable loads. The problem bus(es) and/or net(s) are i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_assertion_r. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-156' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-1669] enum_AREG_0_connects_CEA1_GND_connects_CEA2_GND: stat_regs_inst/i_DSP_cntr: When DSP48E2 attribute AREG is set to 0, the CEA1 and CEA2 pins should be tied to GND to save power. INFO: [DRC REQP-1669] enum_AREG_0_connects_CEA1_GND_connects_CEA2_GND: stat_regs_inst/i_DSP_rate: When DSP48E2 attribute AREG is set to 0, the CEA1 and CEA2 pins should be tied to GND to save power. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [Common 17-14] Message 'DRC REQP-1671' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-1673] enum_BREG_0_connects_CEB1_GND_connects_CEB2_GND: stat_regs_inst/i_DSP_cntr: When DSP48E2 attribute BREG is set to 0, the CEB1 and CEB2 pins should be tied to GND to save power. INFO: [DRC REQP-1673] enum_BREG_0_connects_CEB1_GND_connects_CEB2_GND: stat_regs_inst/i_DSP_rate: When DSP48E2 attribute BREG is set to 0, the CEB1 and CEB2 pins should be tied to GND to save power. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [Common 17-14] Message 'DRC REQP-1675' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [Common 17-14] Message 'DRC REQP-1678' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [Common 17-14] Message 'DRC REQP-1680' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[0].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[10].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[2].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[3].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[4].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[5].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[6].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[7].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[8].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[9].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [Common 17-14] Message 'DRC REQP-1934' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2258 Warnings, 2254 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./ngFEC_top.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-186] 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Sat Mar 13 12:42:57 2021. For additional details about this file, please refer to the WebTalk help file at D:/Xilinx/Vivado/2020.2/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation 744 Infos, 308 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:09:09 ; elapsed = 00:05:53 . Memory (MB): peak = 18451.441 ; gain = 1868.566 INFO: [Common 17-206] Exiting Vivado at Sat Mar 13 12:42:57 2021...