Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 | Date : Sat Mar 13 09:38:32 2021 | Host : baby running 64-bit major release (build 9200) | Command : report_utilization -file ngFEC_top_utilization_placed.rpt -pb ngFEC_top_utilization_placed.pb | Design : ngFEC_top | Device : xcku115flva2104-1 | Design State : Fully Placed --------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. CLB Logic 1.1 Summary of Registers by Type 2. CLB Logic Distribution 3. BLOCKRAM 4. ARITHMETIC 5. I/O 6. CLOCK 7. ADVANCED 8. CONFIGURATION 9. Primitives 10. Black Boxes 11. Instantiated Netlists 12. SLR Connectivity 13. SLR Connectivity Matrix 14. SLR CLB Logic and Dedicated Block Utilization 15. SLR IO Utilization 1. CLB Logic ------------ +----------------------------+--------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------------+--------+-------+-----------+-------+ | CLB LUTs | 429305 | 0 | 663360 | 64.72 | | LUT as Logic | 429142 | 0 | 663360 | 64.69 | | LUT as Memory | 163 | 0 | 293760 | 0.06 | | LUT as Distributed RAM | 40 | 0 | | | | LUT as Shift Register | 123 | 0 | | | | CLB Registers | 388327 | 0 | 1326720 | 29.27 | | Register as Flip Flop | 388327 | 0 | 1326720 | 29.27 | | Register as Latch | 0 | 0 | 1326720 | 0.00 | | CARRY8 | 8780 | 0 | 82920 | 10.59 | | F7 Muxes | 1057 | 0 | 331680 | 0.32 | | F8 Muxes | 0 | 0 | 165840 | 0.00 | | F9 Muxes | 0 | 0 | 82920 | 0.00 | +----------------------------+--------+-------+-----------+-------+ 1.1 Summary of Registers by Type -------------------------------- +--------+--------------+-------------+--------------+ | Total | Clock Enable | Synchronous | Asynchronous | +--------+--------------+-------------+--------------+ | 0 | _ | - | - | | 0 | _ | - | Set | | 0 | _ | - | Reset | | 0 | _ | Set | - | | 0 | _ | Reset | - | | 0 | Yes | - | - | | 19616 | Yes | - | Set | | 189469 | Yes | - | Reset | | 4908 | Yes | Set | - | | 174334 | Yes | Reset | - | +--------+--------------+-------------+--------------+ 2. CLB Logic Distribution ------------------------- +--------------------------------------------+--------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +--------------------------------------------+--------+-------+-----------+-------+ | CLB | 77080 | 0 | 82920 | 92.96 | | CLBL | 42781 | 0 | | | | CLBM | 34299 | 0 | | | | LUT as Logic | 429142 | 0 | 663360 | 64.69 | | using O5 output only | 10040 | | | | | using O6 output only | 303703 | | | | | using O5 and O6 | 115399 | | | | | LUT as Memory | 163 | 0 | 293760 | 0.06 | | LUT as Distributed RAM | 40 | 0 | | | | using O5 output only | 0 | | | | | using O6 output only | 40 | | | | | using O5 and O6 | 0 | | | | | LUT as Shift Register | 123 | 0 | | | | using O5 output only | 0 | | | | | using O6 output only | 75 | | | | | using O5 and O6 | 48 | | | | | CLB Registers | 388327 | 0 | 1326720 | 29.27 | | Register driven from within the CLB | 231636 | | | | | Register driven from outside the CLB | 156691 | | | | | LUT in front of the register is unused | 104729 | | | | | LUT in front of the register is used | 51962 | | | | | Unique Control Sets | 20801 | | 165840 | 12.54 | +--------------------------------------------+--------+-------+-----------+-------+ * * Note: Available Control Sets calculated as Slices * 2, Review the Control Sets Report for more information regarding control sets. 3. BLOCKRAM ----------- +-------------------+--------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------+--------+-------+-----------+-------+ | Block RAM Tile | 1757.5 | 0 | 2160 | 81.37 | | RAMB36/FIFO* | 1417 | 0 | 2160 | 65.60 | | FIFO36E2 only | 1 | | | | | RAMB36E2 only | 1416 | | | | | RAMB18 | 681 | 0 | 4320 | 15.76 | | RAMB18E2 only | 681 | | | | +-------------------+--------+-------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2 4. ARITHMETIC ------------- +----------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------+------+-------+-----------+-------+ | DSPs | 1003 | 0 | 5520 | 18.17 | | DSP48E2 only | 1003 | | | | +----------------+------+-------+-----------+-------+ 5. I/O ------ +------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +------------------+------+-------+-----------+-------+ | Bonded IOB | 44 | 44 | 832 | 5.29 | | HPIOB | 0 | 0 | 676 | 0.00 | | HRIO | 44 | 44 | 156 | 28.21 | | INPUT | 16 | | | | | OUTPUT | 10 | | | | | BIDIR | 18 | | | | | HPIOBDIFFINBUF | 0 | 0 | 480 | 0.00 | | HPIOBDIFFOUTBUF | 0 | 0 | 480 | 0.00 | | HRIODIFFINBUF | 0 | 0 | 72 | 0.00 | | HRIODIFFOUTBUF | 0 | 0 | 72 | 0.00 | | BITSLICE_CONTROL | 0 | 0 | 192 | 0.00 | | BITSLICE_RX_TX | 0 | 0 | 1248 | 0.00 | | BITSLICE_TX | 0 | 0 | 192 | 0.00 | | RIU_OR | 0 | 0 | 96 | 0.00 | +------------------+------+-------+-----------+-------+ 6. CLOCK -------- +----------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------+------+-------+-----------+-------+ | GLOBAL CLOCK BUFFERs | 65 | 0 | 1248 | 5.21 | | BUFGCE | 10 | 0 | 576 | 1.74 | | BUFGCE_DIV | 1 | 0 | 96 | 1.04 | | BUFG_GT | 54 | 0 | 384 | 14.06 | | BUFGCTRL* | 0 | 0 | 192 | 0.00 | | PLLE3_ADV | 0 | 0 | 48 | 0.00 | | MMCME3_ADV | 2 | 0 | 24 | 8.33 | +----------------------+------+-------+-----------+-------+ * Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability. 7. ADVANCED ----------- +-----------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------------+------+-------+-----------+-------+ | GTHE3_CHANNEL | 50 | 50 | 52 | 96.15 | | GTHE3_COMMON | 1 | 0 | 13 | 7.69 | | IBUFDS_GTE3 | 6 | 6 | 26 | 23.08 | | OBUFDS_GTE3 | 1 | 1 | 26 | 3.85 | | OBUFDS_GTE3_ADV | 0 | 0 | 26 | 0.00 | | PCIE_3_1 | 0 | 0 | 6 | 0.00 | | SYSMONE1 | 0 | 0 | 2 | 0.00 | +-----------------+------+-------+-----------+-------+ 8. CONFIGURATION ---------------- +-------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------+------+-------+-----------+-------+ | BSCANE2 | 0 | 0 | 8 | 0.00 | | DNA_PORTE2 | 0 | 0 | 2 | 0.00 | | EFUSE_USR | 0 | 0 | 2 | 0.00 | | FRAME_ECCE3 | 0 | 0 | 2 | 0.00 | | ICAPE3 | 0 | 0 | 4 | 0.00 | | MASTER_JTAG | 0 | 0 | 2 | 0.00 | | STARTUPE3 | 0 | 0 | 2 | 0.00 | +-------------+------+-------+-----------+-------+ 9. Primitives ------------- +---------------+--------+---------------------+ | Ref Name | Used | Functional Category | +---------------+--------+---------------------+ | FDCE | 189469 | Register | | FDRE | 174334 | Register | | LUT6 | 151749 | CLB | | LUT3 | 105566 | CLB | | LUT4 | 101282 | CLB | | LUT5 | 93038 | CLB | | LUT2 | 65950 | CLB | | LUT1 | 26956 | CLB | | FDPE | 19616 | Register | | CARRY8 | 8780 | CLB | | FDSE | 4908 | Register | | RAMB36E2 | 1416 | BLOCKRAM | | MUXF7 | 1057 | CLB | | DSP48E2 | 1003 | Arithmetic | | RAMB18E2 | 681 | BLOCKRAM | | SRL16E | 164 | CLB | | BUFG_GT | 54 | Clock | | BUFG_GT_SYNC | 53 | Clock | | GTHE3_CHANNEL | 50 | Advanced | | RAMD64E | 40 | CLB | | INBUF | 34 | I/O | | IBUFCTRL | 34 | Others | | OBUFT | 18 | I/O | | OBUF | 10 | I/O | | BUFGCE | 10 | Clock | | SRLC32E | 7 | CLB | | IBUFDS_GTE3 | 6 | Advanced | | MMCME3_ADV | 2 | Clock | | OBUFDS_GTE3 | 1 | Advanced | | GTHE3_COMMON | 1 | Advanced | | FIFO36E2 | 1 | BLOCKRAM | | BUFGCE_DIV | 1 | Clock | +---------------+--------+---------------------+ 10. Black Boxes --------------- +----------+------+ | Ref Name | Used | +----------+------+ 11. Instantiated Netlists ------------------------- +----------------------+------+ | Ref Name | Used | +----------------------+------+ | mgt_ip | 48 | | ttc_mgt | 1 | | axi_chip2chip_64B66B | 1 | | aurora_64b66b_0 | 1 | +----------------------+------+ 12. SLR Connectivity -------------------- +----------------------------------+------+-------+-----------+-------+ | | Used | Fixed | Available | Util% | +----------------------------------+------+-------+-----------+-------+ | SLR1 <-> SLR0 | 3518 | | 17280 | 20.36 | | SLR0 -> SLR1 | 2141 | | | 12.39 | | Using TX_REG only | 0 | 0 | | | | Using RX_REG only | 0 | 0 | | | | Using Both TX_REG and RX_REG | 0 | 0 | | | | SLR1 -> SLR0 | 1377 | | | 7.97 | | Using TX_REG only | 0 | 0 | | | | Using RX_REG only | 0 | 0 | | | | Using Both TX_REG and RX_REG | 0 | 0 | | | +----------------------------------+------+-------+-----------+-------+ | Total SLLs Used | 3518 | | | | +----------------------------------+------+-------+-----------+-------+ 13. SLR Connectivity Matrix --------------------------- +-----------+------+------+ | FROM \ TO | SLR1 | SLR0 | +-----------+------+------+ | SLR1 | 0 | 1377 | | SLR0 | 2141 | 0 | +-----------+------+------+ 14. SLR CLB Logic and Dedicated Block Utilization ------------------------------------------------- +----------------------------+--------+--------+--------+--------+ | Site Type | SLR0 | SLR1 | SLR0 % | SLR1 % | +----------------------------+--------+--------+--------+--------+ | CLB | 36590 | 40490 | 88.25 | 97.66 | | CLBL | 20233 | 22548 | 87.59 | 97.61 | | CLBM | 16357 | 17942 | 89.09 | 97.72 | | CLB LUTs | 202748 | 226557 | 61.13 | 68.31 | | LUT as Logic | 202611 | 226531 | 61.09 | 68.30 | | using O5 output only | 4905 | 5135 | 1.48 | 1.55 | | using O6 output only | 143674 | 160029 | 43.32 | 48.25 | | using O5 and O6 | 54032 | 61367 | 16.29 | 18.50 | | LUT as Memory | 137 | 26 | 0.09 | 0.02 | | LUT as Distributed RAM | 40 | 0 | 0.03 | 0.00 | | LUT as Shift Register | 97 | 26 | 0.07 | 0.02 | | using O5 output only | 0 | 0 | 0.00 | 0.00 | | using O6 output only | 49 | 26 | 0.03 | 0.02 | | using O5 and O6 | 48 | 0 | 0.03 | 0.00 | | CLB Registers | 172434 | 215893 | 25.99 | 32.55 | | CARRY8 | 4145 | 4635 | 10.00 | 11.18 | | F7 Muxes | 505 | 552 | 0.30 | 0.33 | | F8 Muxes | 0 | 0 | 0.00 | 0.00 | | F9 Muxes | 0 | 0 | 0.00 | 0.00 | | Block RAM Tile | 819.5 | 938 | 75.88 | 86.85 | | RAMB36/FIFO | 661 | 756 | 61.20 | 70.00 | | RAMB36E2 only | 660 | 756 | 61.11 | 70.00 | | RAMB18 | 317 | 364 | 14.68 | 16.85 | | RAMB18E2 only | 317 | 364 | 14.68 | 16.85 | | URAM | 0 | 0 | 0.00 | 0.00 | | DSPs | 4 | 999 | 0.14 | 36.20 | | PLL | 0 | 0 | 0.00 | 0.00 | | MMCM | 0 | 0 | 0.00 | 0.00 | | Unique Control Sets | 9786 | 11065 | 11.80 | 13.34 | +----------------------------+--------+--------+--------+--------+ * Note: Available Control Sets based on CLB Registers / 8 15. SLR IO Utilization ---------------------- +-----------+-----------+---------+------------+----------+------------+----------+-----+ | SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs | +-----------+-----------+---------+------------+----------+------------+----------+-----+ | SLR1 | 12 | 2.88 | 0 | 0.00 | 0 | 0.00 | 24 | | SLR0 | 32 | 7.69 | 0 | 0.00 | 0 | 0.00 | 26 | +-----------+-----------+---------+------------+----------+------------+----------+-----+ | Total | 44 | | 0 | | 0 | | 50 | +-----------+-----------+---------+------------+----------+------------+----------+-----+