Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 | Date : Sat Mar 13 12:23:59 2021 | Host : baby running 64-bit major release (build 9200) | Command : report_methodology -file ngFEC_top_methodology_drc_routed.rpt -pb ngFEC_top_methodology_drc_routed.pb -rpx ngFEC_top_methodology_drc_routed.rpx | Design : ngFEC_top | Device : xcku115-flva2104-1-c | Speed File : -1 | Design State : Fully Routed ----------------------------------------------------------------------------------------------------------------------------------------------------------------- Report Methodology Table of Contents ----------------- 1. REPORT SUMMARY 2. REPORT DETAILS 1. REPORT SUMMARY ----------------- Netlist: netlist Floorplan: design_1 Design limits: Max violations: Violations found: 5290 +-----------+------------------+-------------------------------------------------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+------------------+-------------------------------------------------------------------+------------+ | TIMING-2 | Critical Warning | Invalid primary clock source pin | 6 | | TIMING-3 | Critical Warning | Invalid primary clock on Clock Modifying Block | 1 | | TIMING-4 | Critical Warning | Invalid primary clock redefinition on a clock tree | 6 | | TIMING-6 | Critical Warning | No common primary clock between related clocks | 3 | | TIMING-7 | Critical Warning | No common node between related clocks | 3 | | AVAL-324 | Warning | Hard_blocks_needs_LOCs | 1 | | DPIR-2 | Warning | Asynchronous driver check | 4097 | | LUTAR-1 | Warning | LUT drives async reset alert | 496 | | SYNTH-11 | Warning | DSP output not registered | 218 | | SYNTH-12 | Warning | DSP input not registered | 384 | | SYNTH-13 | Warning | combinational multiplier | 9 | | TIMING-9 | Warning | Unknown CDC Logic | 1 | | TIMING-10 | Warning | Missing property on synchronizer | 1 | | TIMING-18 | Warning | Missing input or output delay | 44 | | TIMING-24 | Warning | Overridden Max delay datapath only | 11 | | TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 1 | | ULMTCS-1 | Warning | Control Sets use limits recommend reduction | 1 | | XDCB-1 | Warning | Runtime intensive exceptions | 2 | | CLKC-27 | Advisory | MMCME3 with BUF_IN drives sequential IO not with CLKOUT0 | 1 | | CLKC-29 | Advisory | MMCME3 not driven by IO has BUFG in feedback loop | 2 | | CLKC-55 | Advisory | MMCME3 with global clock driver has no LOC | 2 | +-----------+------------------+-------------------------------------------------------------------+------------+ 2. REPORT DETAILS ----------------- TIMING-2#1 Critical Warning Invalid primary clock source pin A primary clock DRPclk is created on an inappropriate pin i_DRPclk_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#2 Critical Warning Invalid primary clock source pin A primary clock clk125 is created on an inappropriate pin i_clk125_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#3 Critical Warning Invalid primary clock source pin A primary clock clk250 is created on an inappropriate pin i_clk250_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#4 Critical Warning Invalid primary clock source pin A primary clock fabric_clk is created on an inappropriate pin fabric_clk_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#5 Critical Warning Invalid primary clock source pin A primary clock ipb_clk is created on an inappropriate pin i_ipb_clk_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#6 Critical Warning Invalid primary clock source pin A primary clock tx_wordclk is created on an inappropriate pin tx_wordclk_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-3#1 Critical Warning Invalid primary clock on Clock Modifying Block A primary clock TTC_rxusrclk is created on the output pin or net i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O of a Clock Modifying Block Related violations: TIMING-4#1 Critical Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock DRPclk is defined downstream of clock DRPclk_dcm and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#2 Critical Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock clk125 is defined downstream of clock clk125_dcm and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#3 Critical Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock clk250 is defined downstream of clock clk250_dcm and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#4 Critical Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock fabric_clk is defined downstream of clock fabric_clk_dcm and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#5 Critical Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock ipb_clk is defined downstream of clock ipb_clk_dcm and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#6 Critical Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock tx_wordclk is defined downstream of clock tx_wordclk_dcm and overrides its insertion delay and/or waveform definition Related violations: TIMING-6#1 Critical Warning No common primary clock between related clocks The clocks clk250 and ipb_clk are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk250] -to [get_clocks ipb_clk] Related violations: TIMING-6#2 Critical Warning No common primary clock between related clocks The clocks fabric_clk and tx_wordclk are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks fabric_clk] -to [get_clocks tx_wordclk] Related violations: TIMING-6#3 Critical Warning No common primary clock between related clocks The clocks ipb_clk and clk250 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks ipb_clk] -to [get_clocks clk250] Related violations: TIMING-7#1 Critical Warning No common node between related clocks The clocks clk250 and ipb_clk are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk250] -to [get_clocks ipb_clk] Related violations: TIMING-7#2 Critical Warning No common node between related clocks The clocks fabric_clk and tx_wordclk are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks fabric_clk] -to [get_clocks tx_wordclk] Related violations: TIMING-7#3 Critical Warning No common node between related clocks The clocks ipb_clk and clk250 are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks ipb_clk] -to [get_clocks clk250] Related violations: AVAL-324#1 Warning Hard_blocks_needs_LOCs The hard block GTHE3_COMMON cell i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST is missing a valid LOC constraint for placement assignment, normally supplied by IP generation or manually assigned using the LOC property. Unguided placement of this block may cause problems in routing. Please set a valid LOC for this block to avoid these problem. Related violations: DPIR-2#1 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#5 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#6 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#7 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#8 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#9 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#10 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#11 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#12 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#13 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#14 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#15 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#16 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#17 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#18 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#19 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#20 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#21 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#22 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#23 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#24 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#25 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#26 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#27 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#28 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#29 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#30 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#31 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#32 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#33 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#34 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#35 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#36 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#37 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#38 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#39 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#40 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#41 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#42 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#43 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#44 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#45 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#46 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#47 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#48 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#49 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#50 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#51 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#52 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#53 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#54 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#55 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#56 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#57 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#58 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#59 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#60 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#61 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#62 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#63 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#64 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#65 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#66 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#67 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#68 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#69 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#70 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#71 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#72 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#73 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#74 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#75 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#76 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#77 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#78 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#79 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#80 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#81 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#82 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#83 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#84 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#85 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#86 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#87 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#88 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#89 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#90 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#91 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#92 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#93 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#94 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#95 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#96 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#97 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#98 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#99 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#100 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#101 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#102 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#103 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#104 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#105 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#106 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#107 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#108 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#109 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#110 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#111 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#112 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#113 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#114 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#115 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#116 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#117 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#118 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#119 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#120 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#121 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#122 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#123 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#124 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#125 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#126 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#127 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#128 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#129 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#130 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#131 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#132 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#133 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#134 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#135 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#136 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#137 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#138 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#139 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#140 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#141 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#142 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#143 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#144 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#145 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#146 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#147 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#148 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#149 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#150 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#151 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#152 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#153 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#154 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#155 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#156 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#157 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#158 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#159 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#160 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#161 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#162 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#163 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#164 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#165 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#166 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#167 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#168 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#169 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#170 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#171 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#172 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#173 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#174 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#175 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#176 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#177 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#178 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#179 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#180 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#181 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#182 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#183 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#184 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#185 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#186 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#187 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#188 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#189 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#190 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#191 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#192 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#193 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#194 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#195 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#196 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#197 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#198 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#199 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#200 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#201 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#202 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#203 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#204 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#205 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#206 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#207 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#208 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#209 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#210 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#211 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#212 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#213 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#214 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#215 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#216 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#217 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#218 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#219 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#220 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#221 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#222 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#223 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#224 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#225 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#226 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#227 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#228 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#229 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#230 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#231 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#232 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#233 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#234 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#235 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#236 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#237 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#238 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#239 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#240 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#241 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#242 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#243 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#244 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#245 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#246 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#247 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#248 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#249 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#250 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#251 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#252 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#253 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#254 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#255 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#256 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#257 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#258 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#259 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#260 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#261 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#262 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#263 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#264 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#265 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#266 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#267 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#268 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#269 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#270 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#271 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#272 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#273 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#274 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#275 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#276 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#277 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#278 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#279 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#280 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#281 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#282 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#283 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#284 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#285 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#286 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#287 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#288 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#289 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#290 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#291 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#292 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#293 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#294 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#295 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#296 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#297 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#298 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#299 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#300 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#301 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#302 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#303 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#304 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#305 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#306 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#307 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#308 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#309 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#310 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#311 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#312 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#313 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#314 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#315 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#316 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#317 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#318 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#319 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#320 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#321 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#322 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#323 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#324 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#325 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#326 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#327 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#328 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#329 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#330 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#331 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#332 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#333 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#334 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#335 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#336 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#337 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#338 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#339 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#340 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#341 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#342 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#343 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#344 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#345 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#346 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#347 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#348 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#349 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#350 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#351 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#352 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#353 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#354 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#355 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#356 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#357 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#358 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#359 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#360 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#361 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#362 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#363 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#364 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#365 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#366 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#367 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#368 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#369 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#370 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#371 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#372 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#373 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#374 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#375 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#376 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#377 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#378 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#379 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#380 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#381 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#382 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#383 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#384 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#385 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#386 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#387 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#388 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#389 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#390 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#391 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#392 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#393 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#394 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#395 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#396 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#397 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#398 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#399 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#400 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#401 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#402 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#403 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#404 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#405 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#406 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#407 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#408 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#409 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#410 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#411 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#412 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#413 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#414 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#415 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#416 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#417 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#418 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#419 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#420 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#421 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#422 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#423 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#424 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#425 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#426 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#427 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#428 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#429 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#430 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#431 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#432 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#433 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#434 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#435 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#436 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#437 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#438 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#439 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#440 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#441 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#442 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#443 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#444 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#445 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#446 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#447 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#448 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#449 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#450 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#451 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#452 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#453 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#454 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#455 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#456 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#457 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#458 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#459 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#460 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#461 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#462 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#463 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#464 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#465 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#466 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#467 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#468 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#469 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#470 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#471 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#472 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#473 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#474 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#475 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#476 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#477 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#478 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#479 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#480 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#481 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#482 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#483 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#484 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#485 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#486 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#487 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#488 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#489 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#490 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#491 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#492 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#493 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#494 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#495 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#496 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#497 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#498 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#499 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#500 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#501 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#502 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#503 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#504 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#505 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#506 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#507 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#508 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#509 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#510 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#511 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#512 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#513 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#514 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#515 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#516 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#517 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#518 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#519 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#520 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#521 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#522 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#523 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#524 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#525 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#526 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#527 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#528 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#529 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#530 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#531 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#532 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#533 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#534 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#535 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#536 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#537 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#538 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#539 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#540 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#541 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#542 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#543 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#544 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#545 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#546 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#547 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#548 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#549 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#550 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#551 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#552 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#553 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#554 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#555 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#556 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#557 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#558 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#559 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#560 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#561 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#562 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#563 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#564 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#565 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#566 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#567 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#568 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#569 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#570 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#571 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#572 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#573 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#574 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#575 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#576 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#577 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#578 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#579 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#580 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#581 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#582 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#583 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#584 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#585 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#586 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#587 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#588 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#589 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#590 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#591 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#592 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#593 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#594 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#595 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#596 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#597 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#598 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#599 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#600 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#601 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#602 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#603 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#604 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#605 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#606 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#607 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#608 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#609 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#610 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#611 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#612 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#613 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#614 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#615 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#616 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#617 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#618 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#619 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#620 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#621 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#622 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#623 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#624 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#625 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#626 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#627 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#628 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#629 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#630 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#631 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#632 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#633 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#634 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#635 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#636 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#637 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#638 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#639 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#640 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#641 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#642 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#643 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#644 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#645 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#646 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#647 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#648 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#649 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#650 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#651 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#652 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#653 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#654 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#655 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#656 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#657 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#658 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#659 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#660 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#661 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#662 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#663 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#664 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#665 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#666 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#667 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#668 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#669 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#670 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#671 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#672 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#673 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#674 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#675 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#676 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#677 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#678 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#679 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#680 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#681 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#682 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#683 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#684 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#685 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#686 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#687 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#688 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#689 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#690 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#691 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#692 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#693 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#694 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#695 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#696 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#697 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#698 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#699 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#700 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#701 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#702 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#703 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#704 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#705 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#706 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#707 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#708 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#709 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#710 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#711 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#712 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#713 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#714 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#715 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#716 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#717 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#718 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#719 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#720 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#721 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#722 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#723 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#724 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#725 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#726 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#727 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#728 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#729 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#730 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#731 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#732 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#733 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#734 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#735 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#736 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#737 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#738 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#739 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#740 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#741 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#742 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#743 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#744 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#745 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#746 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#747 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#748 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#749 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#750 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#751 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#752 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#753 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#754 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#755 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#756 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#757 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#758 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#759 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#760 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#761 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#762 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#763 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#764 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#765 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#766 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#767 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#768 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#769 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#770 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#771 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#772 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#773 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#774 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#775 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#776 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#777 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#778 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#779 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#780 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#781 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#782 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#783 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#784 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#785 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#786 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#787 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#788 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#789 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#790 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#791 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#792 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#793 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#794 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#795 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#796 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#797 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#798 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#799 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#800 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#801 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#802 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#803 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#804 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#805 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#806 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#807 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#808 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#809 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#810 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#811 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#812 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#813 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#814 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#815 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#816 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#817 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#818 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#819 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#820 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#821 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#822 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#823 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#824 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#825 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#826 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#827 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#828 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#829 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#830 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#831 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#832 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#833 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#834 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#835 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#836 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#837 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#838 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#839 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#840 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#841 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#842 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#843 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#844 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#845 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#846 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#847 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#848 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#849 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#850 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#851 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#852 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#853 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#854 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#855 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#856 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#857 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#858 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#859 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#860 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#861 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#862 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#863 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#864 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#865 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#866 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#867 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#868 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#869 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#870 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#871 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#872 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#873 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#874 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#875 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#876 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#877 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#878 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#879 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#880 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#881 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#882 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#883 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#884 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#885 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#886 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#887 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#888 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#889 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#890 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#891 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#892 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#893 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#894 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#895 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#896 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#897 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#898 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#899 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#900 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#901 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#902 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#903 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#904 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#905 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#906 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#907 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#908 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#909 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#910 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#911 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#912 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#913 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#914 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#915 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#916 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#917 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#918 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#919 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#920 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#921 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#922 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#923 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#924 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#925 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#926 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#927 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#928 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#929 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#930 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#931 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#932 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#933 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#934 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#935 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#936 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#937 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#938 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#939 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#940 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#941 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#942 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#943 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#944 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#945 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#946 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#947 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#948 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#949 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#950 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#951 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#952 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#953 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#954 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#955 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#956 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#957 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#958 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#959 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#960 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#961 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#962 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#963 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#964 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#965 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#966 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#967 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#968 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#969 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#970 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#971 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#972 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#973 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#974 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#975 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#976 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#977 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#978 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#979 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#980 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#981 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#982 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#983 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#984 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#985 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#986 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#987 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#988 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#989 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#990 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#991 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#992 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#993 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#994 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#995 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#996 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#997 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#998 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#999 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1000 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1001 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1002 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1003 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1004 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1005 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1006 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1007 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1008 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1009 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1010 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1011 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1012 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1013 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1014 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1015 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1016 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1017 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1018 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1019 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1020 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1021 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1022 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1023 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1024 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1025 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1026 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1027 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1028 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1029 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1030 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1031 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1032 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1033 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1034 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1035 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1036 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1037 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1038 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1039 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1040 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1041 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1042 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1043 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1044 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1045 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1046 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1047 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1048 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1049 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1050 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1051 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1052 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1053 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1054 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1055 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1056 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1057 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1058 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1059 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1060 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1061 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1062 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1063 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1064 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1065 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1066 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1067 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1068 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1069 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1070 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1071 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1072 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1073 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1074 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1075 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1076 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1077 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1078 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1079 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1080 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1081 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1082 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1083 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1084 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1085 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1086 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1087 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1088 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1089 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1090 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1091 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1092 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1093 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1094 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1095 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1096 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1097 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1098 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1099 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1100 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1101 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1102 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1103 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1104 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1105 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1106 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1107 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1108 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1109 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1110 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1111 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1112 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1113 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1114 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1115 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1116 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1117 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1118 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1119 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1120 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1121 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1122 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1123 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1124 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1125 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1126 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1127 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1128 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1129 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1130 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1131 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1132 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1133 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1134 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1135 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1136 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1137 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1138 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1139 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1140 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1141 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1142 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1143 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1144 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1145 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1146 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1147 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1148 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1149 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1150 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1151 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1152 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1153 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1154 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1155 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1156 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1157 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1158 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1159 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1160 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1161 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1162 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1163 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1164 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1165 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1166 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1167 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1168 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1169 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1170 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1171 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1172 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1173 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1174 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1175 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1176 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1177 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1178 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1179 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1180 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1181 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1182 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1183 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1184 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1185 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1186 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1187 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1188 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1189 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1190 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1191 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1192 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1193 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1194 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1195 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1196 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1197 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1198 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1199 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1200 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1201 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1202 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1203 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1204 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1205 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1206 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1207 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1208 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1209 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1210 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1211 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1212 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1213 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1214 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1215 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1216 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1217 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1218 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1219 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1220 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1221 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1222 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1223 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1224 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1225 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1226 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1227 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1228 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1229 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1230 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1231 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1232 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1233 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1234 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1235 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1236 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1237 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1238 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1239 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1240 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1241 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1242 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1243 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1244 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1245 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1246 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1247 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1248 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1249 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1250 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1251 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1252 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1253 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1254 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1255 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1256 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1257 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1258 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1259 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1260 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1261 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1262 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1263 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1264 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1265 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1266 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1267 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1268 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1269 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1270 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1271 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1272 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1273 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1274 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1275 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1276 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1277 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1278 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1279 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1280 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1281 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1282 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1283 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1284 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1285 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1286 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1287 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1288 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1289 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1290 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1291 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1292 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1293 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1294 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1295 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1296 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1297 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1298 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1299 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1300 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1301 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1302 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1303 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1304 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1305 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1306 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1307 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1308 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1309 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1310 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1311 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1312 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1313 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1314 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1315 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1316 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1317 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1318 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1319 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1320 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1321 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1322 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1323 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1324 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1325 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1326 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1327 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1328 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1329 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1330 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1331 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1332 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1333 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1334 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1335 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1336 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1337 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1338 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1339 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1340 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1341 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1342 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1343 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1344 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1345 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1346 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1347 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1348 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1349 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1350 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1351 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1352 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1353 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1354 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1355 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1356 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1357 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1358 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1359 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1360 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1361 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1362 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1363 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1364 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1365 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1366 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1367 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1368 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1369 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1370 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1371 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1372 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1373 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1374 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1375 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1376 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1377 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1378 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1379 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1380 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1381 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1382 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1383 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1384 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1385 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1386 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1387 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1388 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1389 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1390 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1391 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1392 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1393 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1394 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1395 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1396 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1397 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1398 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1399 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1400 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1401 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1402 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1403 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1404 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1405 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1406 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1407 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1408 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1409 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1410 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1411 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1412 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1413 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1414 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1415 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1416 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1417 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1418 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1419 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1420 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1421 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1422 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1423 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1424 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1425 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1426 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1427 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1428 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1429 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1430 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1431 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1432 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1433 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1434 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1435 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1436 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1437 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1438 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1439 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1440 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1441 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1442 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1443 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1444 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1445 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1446 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1447 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1448 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1449 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1450 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1451 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1452 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1453 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1454 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1455 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1456 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1457 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1458 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1459 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1460 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1461 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1462 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1463 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1464 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1465 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1466 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1467 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1468 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1469 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1470 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1471 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1472 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1473 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1474 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1475 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1476 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1477 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1478 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1479 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1480 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1481 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1482 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1483 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1484 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1485 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1486 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1487 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1488 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1489 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1490 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1491 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1492 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1493 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1494 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1495 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1496 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1497 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1498 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1499 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1500 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1501 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1502 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1503 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1504 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1505 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1506 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1507 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1508 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1509 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1510 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1511 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1512 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1513 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1514 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1515 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1516 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1517 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1518 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1519 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1520 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1521 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1522 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1523 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1524 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1525 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1526 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1527 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1528 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1529 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1530 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1531 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1532 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1533 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1534 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1535 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1536 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1537 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1538 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1539 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1540 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1541 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1542 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1543 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1544 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1545 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1546 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1547 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1548 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1549 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1550 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1551 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1552 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1553 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1554 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1555 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1556 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1557 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1558 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1559 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1560 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1561 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1562 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1563 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1564 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1565 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1566 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1567 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1568 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1569 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1570 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1571 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1572 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1573 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1574 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1575 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1576 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1577 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1578 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1579 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1580 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1581 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1582 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1583 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1584 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1585 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1586 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1587 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1588 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1589 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1590 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1591 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1592 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1593 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1594 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1595 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1596 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1597 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1598 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1599 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1600 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1601 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1602 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1603 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1604 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1605 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1606 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1607 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1608 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1609 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1610 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1611 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1612 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1613 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1614 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1615 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1616 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1617 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1618 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1619 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1620 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1621 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1622 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1623 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1624 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1625 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1626 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1627 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1628 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1629 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1630 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1631 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1632 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1633 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1634 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1635 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1636 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1637 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1638 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1639 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1640 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1641 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1642 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1643 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1644 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1645 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1646 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1647 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1648 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1649 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1650 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1651 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1652 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1653 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1654 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1655 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1656 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1657 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1658 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1659 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1660 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1661 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1662 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1663 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1664 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1665 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1666 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1667 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1668 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1669 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1670 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1671 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1672 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1673 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1674 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1675 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1676 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1677 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1678 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1679 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1680 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1681 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1682 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1683 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1684 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1685 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1686 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1687 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1688 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1689 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1690 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1691 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1692 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1693 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1694 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1695 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1696 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1697 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1698 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1699 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1700 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1701 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1702 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1703 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1704 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1705 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1706 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1707 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1708 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1709 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1710 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1711 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1712 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1713 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1714 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1715 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1716 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1717 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1718 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1719 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1720 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1721 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1722 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1723 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1724 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1725 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1726 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1727 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1728 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1729 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1730 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1731 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1732 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1733 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1734 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1735 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1736 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1737 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1738 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1739 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1740 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1741 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1742 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1743 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1744 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1745 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1746 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1747 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1748 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1749 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1750 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1751 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1752 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1753 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1754 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1755 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1756 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1757 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1758 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1759 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1760 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1761 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1762 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1763 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1764 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1765 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1766 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1767 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1768 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1769 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1770 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1771 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1772 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1773 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1774 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1775 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1776 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1777 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1778 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1779 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1780 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1781 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1782 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1783 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1784 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1785 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1786 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1787 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1788 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1789 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1790 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1791 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1792 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1793 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1794 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1795 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1796 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1797 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1798 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1799 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1800 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1801 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1802 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1803 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1804 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1805 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1806 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1807 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1808 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1809 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1810 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1811 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1812 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1813 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1814 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1815 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1816 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1817 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1818 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1819 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1820 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1821 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1822 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1823 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1824 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1825 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1826 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1827 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1828 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1829 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1830 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1831 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1832 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1833 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1834 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1835 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1836 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1837 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1838 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1839 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1840 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1841 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1842 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1843 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1844 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1845 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1846 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1847 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1848 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1849 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1850 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1851 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1852 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1853 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1854 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1855 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1856 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1857 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1858 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1859 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1860 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1861 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1862 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1863 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1864 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1865 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1866 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1867 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1868 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1869 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1870 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1871 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1872 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1873 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1874 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1875 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1876 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1877 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1878 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1879 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1880 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1881 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1882 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1883 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1884 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1885 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1886 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1887 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1888 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1889 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1890 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1891 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1892 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1893 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1894 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1895 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1896 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1897 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1898 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1899 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1900 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1901 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1902 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1903 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1904 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1905 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1906 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1907 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1908 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1909 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1910 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1911 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1912 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1913 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1914 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1915 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1916 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1917 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1918 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1919 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1920 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1921 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1922 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1923 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1924 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1925 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1926 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1927 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1928 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1929 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1930 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1931 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1932 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1933 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1934 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1935 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1936 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1937 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1938 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1939 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1940 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1941 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1942 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1943 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1944 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1945 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1946 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1947 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1948 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1949 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1950 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1951 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1952 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1953 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1954 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1955 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1956 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1957 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1958 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1959 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1960 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1961 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1962 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1963 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1964 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1965 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1966 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1967 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1968 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1969 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1970 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1971 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1972 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1973 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1974 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1975 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1976 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1977 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1978 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1979 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1980 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1981 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1982 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1983 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1984 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1985 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1986 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1987 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1988 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1989 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1990 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1991 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1992 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1993 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1994 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1995 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1996 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1997 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1998 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#1999 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2000 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2001 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2002 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2003 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2004 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2005 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2006 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2007 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2008 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2009 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2010 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2011 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2012 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2013 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2014 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2015 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2016 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2017 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2018 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2019 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2020 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2021 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2022 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2023 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2024 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2025 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2026 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2027 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2028 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2029 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2030 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2031 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2032 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2033 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2034 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2035 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2036 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2037 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2038 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2039 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2040 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2041 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2042 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2043 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2044 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2045 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2046 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2047 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2048 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2049 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2050 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2051 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2052 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2053 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2054 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2055 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2056 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2057 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2058 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2059 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2060 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2061 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2062 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2063 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2064 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2065 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2066 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2067 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2068 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2069 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2070 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2071 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2072 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2073 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2074 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2075 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2076 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2077 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2078 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2079 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2080 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2081 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2082 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2083 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2084 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2085 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2086 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2087 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2088 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2089 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2090 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2091 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2092 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2093 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2094 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2095 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2096 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2097 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2098 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2099 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2100 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2101 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2102 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2103 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2104 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2105 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2106 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2107 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2108 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2109 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2110 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2111 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2112 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2113 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2114 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2115 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2116 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2117 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2118 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2119 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2120 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2121 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2122 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2123 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2124 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2125 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2126 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2127 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2128 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2129 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2130 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2131 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2132 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2133 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2134 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2135 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2136 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2137 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2138 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2139 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2140 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2141 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2142 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2143 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2144 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2145 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2146 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2147 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2148 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2149 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2150 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2151 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2152 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2153 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2154 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2155 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2156 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2157 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2158 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2159 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2160 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2161 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2162 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2163 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2164 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2165 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2166 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2167 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2168 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2169 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2170 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2171 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2172 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2173 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2174 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2175 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2176 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2177 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2178 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2179 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2180 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2181 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2182 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2183 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2184 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2185 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2186 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2187 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2188 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2189 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2190 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2191 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2192 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2193 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2194 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2195 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2196 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2197 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2198 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2199 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2200 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2201 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2202 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2203 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2204 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2205 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2206 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2207 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2208 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2209 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2210 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2211 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2212 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2213 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2214 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2215 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2216 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2217 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2218 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2219 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2220 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2221 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2222 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2223 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2224 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2225 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2226 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2227 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2228 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2229 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2230 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2231 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2232 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2233 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2234 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2235 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2236 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2237 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2238 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2239 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2240 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2241 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2242 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2243 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2244 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2245 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2246 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2247 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2248 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2249 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2250 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2251 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2252 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2253 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2254 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2255 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2256 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2257 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2258 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2259 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2260 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2261 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2262 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2263 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2264 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2265 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2266 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2267 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2268 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2269 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2270 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2271 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2272 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2273 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2274 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2275 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2276 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2277 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2278 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2279 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2280 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2281 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2282 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2283 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2284 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2285 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2286 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2287 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2288 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2289 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2290 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2291 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2292 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2293 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2294 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2295 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2296 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2297 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2298 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2299 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2300 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2301 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2302 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2303 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2304 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2305 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2306 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2307 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2308 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2309 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2310 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2311 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2312 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2313 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2314 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2315 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2316 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2317 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2318 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2319 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2320 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2321 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2322 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2323 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2324 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2325 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2326 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2327 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2328 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2329 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2330 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2331 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2332 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2333 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2334 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2335 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2336 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2337 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2338 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2339 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2340 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2341 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2342 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2343 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2344 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2345 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2346 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2347 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2348 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2349 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2350 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2351 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2352 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2353 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2354 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2355 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2356 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2357 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2358 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2359 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2360 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2361 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2362 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2363 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2364 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2365 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2366 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2367 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2368 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2369 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2370 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2371 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2372 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2373 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2374 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2375 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2376 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2377 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2378 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2379 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2380 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2381 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2382 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2383 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2384 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2385 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2386 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2387 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2388 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2389 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2390 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2391 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2392 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2393 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2394 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2395 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2396 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2397 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2398 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2399 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2400 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2401 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2402 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2403 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2404 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2405 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2406 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2407 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2408 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2409 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2410 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2411 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2412 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2413 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2414 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2415 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2416 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2417 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2418 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2419 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2420 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2421 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2422 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2423 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2424 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2425 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2426 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2427 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2428 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2429 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2430 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2431 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2432 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2433 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2434 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2435 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2436 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2437 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2438 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2439 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2440 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2441 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2442 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2443 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2444 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2445 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2446 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2447 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2448 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2449 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2450 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2451 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2452 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2453 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2454 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2455 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2456 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2457 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2458 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2459 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2460 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2461 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2462 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2463 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2464 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2465 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2466 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2467 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2468 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2469 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2470 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2471 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2472 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2473 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2474 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2475 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2476 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2477 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2478 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2479 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2480 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2481 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2482 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2483 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2484 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2485 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2486 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2487 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2488 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2489 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2490 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2491 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2492 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2493 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2494 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2495 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2496 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2497 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2498 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2499 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2500 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2501 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2502 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2503 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2504 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2505 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2506 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2507 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2508 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2509 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2510 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2511 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2512 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2513 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2514 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2515 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2516 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2517 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2518 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2519 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2520 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2521 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2522 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2523 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2524 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2525 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2526 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2527 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2528 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2529 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2530 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2531 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2532 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2533 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2534 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2535 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2536 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2537 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2538 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2539 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2540 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2541 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2542 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2543 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2544 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2545 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2546 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2547 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2548 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2549 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2550 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2551 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2552 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2553 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2554 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2555 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2556 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2557 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2558 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2559 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2560 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2561 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2562 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2563 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2564 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2565 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2566 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2567 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2568 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2569 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2570 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2571 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2572 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2573 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2574 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2575 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2576 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2577 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2578 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2579 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2580 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2581 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2582 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2583 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2584 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2585 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2586 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2587 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2588 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2589 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2590 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2591 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2592 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2593 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2594 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2595 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2596 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2597 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2598 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2599 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2600 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2601 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2602 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2603 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2604 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2605 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2606 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2607 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2608 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2609 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2610 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2611 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2612 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2613 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2614 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2615 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2616 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2617 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2618 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2619 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2620 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2621 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2622 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2623 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2624 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2625 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2626 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2627 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2628 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2629 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2630 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2631 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2632 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2633 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2634 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2635 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2636 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2637 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2638 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2639 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2640 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2641 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2642 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2643 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2644 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2645 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2646 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2647 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2648 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2649 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2650 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2651 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2652 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2653 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2654 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2655 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2656 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2657 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2658 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2659 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2660 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2661 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2662 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2663 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2664 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2665 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2666 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2667 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2668 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2669 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2670 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2671 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2672 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2673 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2674 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2675 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2676 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2677 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2678 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2679 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2680 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2681 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2682 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2683 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2684 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2685 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2686 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2687 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2688 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2689 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2690 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2691 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2692 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2693 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2694 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2695 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2696 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2697 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2698 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2699 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2700 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2701 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2702 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2703 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2704 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2705 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2706 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2707 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2708 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2709 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2710 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2711 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2712 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2713 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2714 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2715 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2716 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2717 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2718 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2719 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2720 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2721 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2722 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2723 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2724 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2725 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2726 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2727 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2728 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2729 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2730 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2731 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2732 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2733 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2734 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2735 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2736 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2737 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2738 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2739 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2740 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2741 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2742 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2743 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2744 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2745 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2746 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2747 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2748 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2749 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2750 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2751 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2752 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2753 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2754 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2755 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2756 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2757 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2758 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2759 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2760 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2761 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2762 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2763 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2764 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2765 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2766 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2767 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2768 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2769 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2770 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2771 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2772 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2773 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2774 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2775 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2776 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2777 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2778 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2779 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2780 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2781 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2782 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2783 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2784 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2785 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2786 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2787 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2788 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2789 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2790 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2791 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2792 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2793 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2794 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2795 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2796 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2797 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2798 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2799 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2800 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2801 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2802 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2803 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2804 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2805 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2806 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2807 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2808 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2809 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2810 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2811 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2812 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2813 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2814 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2815 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2816 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2817 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2818 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2819 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2820 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2821 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2822 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2823 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2824 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2825 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2826 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2827 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2828 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2829 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2830 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2831 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2832 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2833 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2834 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2835 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2836 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2837 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2838 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2839 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2840 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2841 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2842 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2843 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2844 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2845 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2846 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2847 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2848 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2849 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2850 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2851 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2852 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2853 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2854 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2855 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2856 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2857 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2858 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2859 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2860 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2861 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2862 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2863 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2864 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2865 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2866 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2867 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2868 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2869 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2870 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2871 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2872 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2873 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2874 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2875 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2876 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2877 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2878 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2879 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2880 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2881 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2882 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2883 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2884 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2885 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2886 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2887 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2888 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2889 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2890 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2891 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2892 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2893 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2894 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2895 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2896 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2897 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2898 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2899 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2900 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2901 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2902 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2903 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2904 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2905 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2906 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2907 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2908 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2909 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2910 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2911 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2912 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2913 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2914 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2915 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2916 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2917 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2918 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2919 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2920 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2921 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2922 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2923 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2924 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2925 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2926 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2927 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2928 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2929 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2930 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2931 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2932 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2933 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2934 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2935 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2936 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2937 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2938 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2939 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2940 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2941 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2942 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2943 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2944 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2945 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2946 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2947 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2948 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2949 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2950 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2951 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2952 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2953 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2954 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2955 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2956 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2957 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2958 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2959 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2960 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2961 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2962 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2963 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2964 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2965 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2966 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2967 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2968 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2969 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2970 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2971 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2972 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2973 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2974 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2975 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2976 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2977 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2978 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2979 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2980 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2981 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2982 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2983 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2984 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2985 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2986 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2987 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2988 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2989 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2990 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2991 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2992 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2993 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2994 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2995 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2996 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2997 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2998 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#2999 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3000 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3001 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3002 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3003 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3004 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3005 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3006 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3007 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3008 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3009 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3010 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3011 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3012 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3013 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3014 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3015 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3016 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3017 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3018 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3019 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3020 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3021 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3022 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3023 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3024 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3025 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3026 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3027 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3028 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3029 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3030 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3031 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3032 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3033 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3034 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3035 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3036 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3037 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3038 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3039 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3040 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3041 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3042 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3043 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3044 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3045 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3046 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3047 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3048 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3049 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3050 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3051 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3052 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3053 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3054 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3055 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3056 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3057 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3058 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3059 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3060 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3061 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3062 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3063 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3064 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3065 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3066 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3067 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3068 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3069 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3070 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3071 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3072 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3073 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3074 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3075 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3076 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3077 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3078 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3079 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3080 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3081 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3082 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3083 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3084 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3085 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3086 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3087 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3088 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3089 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3090 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3091 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3092 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3093 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3094 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3095 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3096 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3097 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3098 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3099 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3100 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3101 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3102 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3103 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3104 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3105 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3106 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3107 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3108 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3109 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3110 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3111 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3112 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3113 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3114 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3115 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3116 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3117 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3118 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3119 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3120 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3121 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3122 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3123 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3124 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3125 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3126 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3127 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3128 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3129 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3130 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3131 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3132 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3133 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3134 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3135 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3136 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3137 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3138 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3139 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3140 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3141 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3142 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3143 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3144 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3145 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3146 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3147 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3148 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3149 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3150 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3151 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3152 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3153 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3154 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3155 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3156 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3157 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3158 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3159 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3160 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3161 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3162 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3163 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3164 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3165 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3166 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3167 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3168 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3169 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3170 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3171 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3172 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3173 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3174 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3175 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3176 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3177 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3178 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3179 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3180 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3181 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3182 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3183 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3184 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3185 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3186 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3187 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3188 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3189 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3190 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3191 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3192 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3193 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3194 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3195 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3196 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3197 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3198 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3199 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3200 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3201 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3202 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3203 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3204 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3205 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3206 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3207 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3208 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3209 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3210 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3211 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3212 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3213 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3214 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3215 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3216 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3217 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3218 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3219 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3220 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3221 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3222 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3223 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3224 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3225 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3226 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3227 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3228 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3229 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3230 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3231 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3232 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3233 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3234 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3235 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3236 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3237 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3238 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3239 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3240 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3241 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3242 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3243 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3244 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3245 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3246 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3247 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3248 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3249 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3250 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3251 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3252 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3253 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3254 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3255 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3256 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3257 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3258 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3259 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3260 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3261 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3262 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3263 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3264 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3265 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3266 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3267 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3268 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3269 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3270 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3271 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3272 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3273 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3274 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3275 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3276 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3277 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3278 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3279 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3280 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3281 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3282 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3283 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3284 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3285 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3286 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3287 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3288 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3289 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3290 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3291 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3292 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3293 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3294 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3295 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3296 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3297 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3298 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3299 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3300 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3301 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3302 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3303 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3304 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3305 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3306 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3307 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3308 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3309 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3310 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3311 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3312 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3313 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3314 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3315 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3316 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3317 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3318 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3319 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3320 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3321 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3322 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3323 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3324 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3325 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3326 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3327 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3328 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3329 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3330 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3331 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3332 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3333 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3334 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3335 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3336 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3337 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3338 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3339 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3340 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3341 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3342 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3343 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3344 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3345 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3346 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3347 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3348 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3349 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3350 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3351 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3352 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3353 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3354 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3355 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3356 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3357 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3358 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3359 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3360 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3361 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3362 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3363 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3364 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3365 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3366 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3367 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3368 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3369 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3370 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3371 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3372 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3373 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3374 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3375 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3376 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3377 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3378 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3379 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3380 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3381 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3382 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3383 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3384 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3385 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3386 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3387 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3388 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3389 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3390 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3391 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3392 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3393 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3394 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3395 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3396 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3397 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3398 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3399 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3400 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3401 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3402 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3403 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3404 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3405 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3406 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3407 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3408 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3409 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3410 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3411 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3412 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3413 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3414 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3415 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3416 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3417 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3418 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3419 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3420 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3421 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3422 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3423 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3424 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3425 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3426 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3427 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3428 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3429 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3430 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3431 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3432 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3433 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3434 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3435 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3436 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3437 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3438 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3439 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3440 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3441 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3442 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3443 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3444 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3445 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3446 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3447 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3448 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3449 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3450 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3451 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3452 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3453 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3454 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3455 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3456 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3457 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3458 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3459 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3460 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3461 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3462 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3463 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3464 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3465 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3466 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3467 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3468 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3469 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3470 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3471 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3472 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3473 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3474 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3475 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3476 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3477 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3478 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3479 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3480 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3481 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3482 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3483 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3484 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3485 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3486 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3487 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3488 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3489 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3490 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3491 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3492 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3493 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3494 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3495 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3496 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3497 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3498 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3499 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3500 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3501 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3502 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3503 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3504 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3505 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3506 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3507 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3508 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3509 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3510 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3511 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3512 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3513 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3514 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3515 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3516 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3517 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3518 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3519 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3520 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3521 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3522 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3523 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3524 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3525 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3526 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3527 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3528 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3529 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3530 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3531 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3532 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3533 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3534 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3535 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3536 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3537 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3538 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3539 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3540 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3541 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3542 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3543 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3544 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3545 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3546 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3547 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3548 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3549 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3550 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3551 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3552 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3553 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3554 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3555 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3556 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3557 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3558 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3559 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3560 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3561 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3562 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3563 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3564 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3565 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3566 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3567 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3568 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3569 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3570 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3571 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3572 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3573 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3574 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3575 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3576 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3577 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3578 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3579 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3580 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3581 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3582 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3583 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3584 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3585 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3586 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3587 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3588 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3589 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3590 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3591 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3592 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3593 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3594 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3595 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3596 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3597 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3598 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3599 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3600 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3601 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3602 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3603 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3604 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3605 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3606 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3607 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3608 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3609 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3610 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3611 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3612 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3613 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3614 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3615 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3616 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3617 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3618 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3619 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3620 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3621 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3622 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3623 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3624 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3625 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3626 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3627 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3628 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3629 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3630 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3631 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3632 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3633 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3634 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3635 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3636 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3637 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3638 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3639 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3640 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3641 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3642 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3643 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3644 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3645 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3646 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3647 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3648 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3649 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3650 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3651 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3652 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3653 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3654 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3655 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3656 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3657 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3658 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3659 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3660 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3661 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3662 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3663 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3664 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3665 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3666 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3667 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3668 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3669 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3670 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3671 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3672 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3673 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3674 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3675 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3676 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3677 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3678 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3679 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3680 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3681 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3682 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3683 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3684 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3685 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3686 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3687 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3688 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3689 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3690 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3691 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3692 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3693 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3694 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3695 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3696 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3697 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3698 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3699 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3700 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3701 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3702 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3703 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3704 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3705 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3706 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3707 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3708 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3709 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3710 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3711 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3712 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3713 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3714 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3715 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3716 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3717 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3718 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3719 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3720 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3721 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3722 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3723 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3724 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3725 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3726 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3727 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3728 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3729 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3730 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3731 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3732 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3733 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3734 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3735 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3736 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3737 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3738 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3739 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3740 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3741 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3742 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3743 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3744 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3745 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3746 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3747 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3748 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3749 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3750 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3751 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3752 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3753 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3754 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3755 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3756 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3757 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3758 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3759 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3760 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3761 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3762 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3763 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3764 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3765 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3766 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3767 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3768 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3769 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3770 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3771 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3772 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3773 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3774 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3775 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3776 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3777 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3778 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3779 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3780 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3781 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3782 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3783 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3784 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3785 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3786 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3787 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3788 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3789 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3790 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3791 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3792 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3793 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3794 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3795 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3796 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3797 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3798 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3799 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3800 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3801 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3802 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3803 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3804 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3805 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3806 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3807 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3808 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3809 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3810 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3811 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3812 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3813 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3814 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3815 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3816 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3817 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3818 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3819 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3820 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3821 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3822 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3823 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3824 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3825 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3826 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3827 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3828 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3829 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3830 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3831 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3832 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3833 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3834 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3835 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3836 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3837 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3838 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3839 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3840 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3841 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3842 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3843 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3844 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3845 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3846 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3847 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3848 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3849 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3850 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3851 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3852 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3853 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3854 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3855 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3856 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3857 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3858 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3859 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3860 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3861 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3862 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3863 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3864 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3865 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3866 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3867 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3868 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3869 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3870 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3871 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3872 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3873 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3874 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3875 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3876 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3877 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3878 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3879 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3880 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3881 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3882 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3883 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3884 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3885 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3886 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3887 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3888 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3889 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3890 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3891 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3892 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3893 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3894 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3895 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3896 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3897 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3898 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3899 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3900 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3901 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3902 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3903 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3904 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3905 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3906 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3907 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3908 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3909 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3910 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3911 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3912 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3913 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3914 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3915 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3916 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3917 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3918 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3919 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3920 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3921 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3922 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3923 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3924 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3925 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3926 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3927 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3928 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3929 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3930 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3931 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3932 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3933 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3934 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3935 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3936 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3937 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3938 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3939 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3940 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3941 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3942 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3943 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3944 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3945 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3946 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3947 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3948 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3949 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3950 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3951 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3952 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3953 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3954 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3955 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3956 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3957 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3958 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3959 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3960 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3961 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3962 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3963 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3964 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3965 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3966 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3967 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3968 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3969 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3970 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3971 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3972 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3973 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3974 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3975 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3976 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3977 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3978 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3979 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3980 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3981 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3982 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3983 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3984 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3985 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3986 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3987 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3988 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3989 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3990 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3991 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3992 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3993 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3994 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3995 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3996 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3997 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3998 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#3999 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4000 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4001 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4002 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4003 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4004 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4005 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4006 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4007 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4008 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4009 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4010 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4011 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4012 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4013 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4014 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4015 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4016 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4017 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4018 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4019 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4020 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4021 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4022 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4023 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4024 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4025 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4026 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4027 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4028 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4029 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4030 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4031 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4032 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4033 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4034 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4035 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4036 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4037 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4038 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4039 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4040 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4041 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4042 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4043 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4044 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4045 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4046 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4047 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4048 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4049 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4050 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4051 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4052 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4053 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4054 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4055 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4056 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4057 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4058 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4059 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4060 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4061 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4062 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4063 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4064 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4065 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4066 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4067 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4068 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4069 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4070 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4071 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4072 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4073 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4074 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4075 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4076 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4077 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4078 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4079 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4080 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4081 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4082 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4083 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4084 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4085 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4086 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4087 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4088 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4089 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4090 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4091 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4092 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4093 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4094 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4095 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4096 Warning Asynchronous driver check DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: DPIR-2#4097 Warning Asynchronous driver check DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. Related violations: LUTAR-1#1 Warning LUT drives async reset alert LUT cell SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#2 Warning LUT drives async reset alert LUT cell SFP_GEN[10].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#3 Warning LUT drives async reset alert LUT cell SFP_GEN[11].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#4 Warning LUT drives async reset alert LUT cell SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#5 Warning LUT drives async reset alert LUT cell SFP_GEN[13].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#6 Warning LUT drives async reset alert LUT cell SFP_GEN[14].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#7 Warning LUT drives async reset alert LUT cell SFP_GEN[15].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#8 Warning LUT drives async reset alert LUT cell SFP_GEN[16].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#9 Warning LUT drives async reset alert LUT cell SFP_GEN[17].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#10 Warning LUT drives async reset alert LUT cell SFP_GEN[18].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#11 Warning LUT drives async reset alert LUT cell SFP_GEN[19].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#12 Warning LUT drives async reset alert LUT cell SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#13 Warning LUT drives async reset alert LUT cell SFP_GEN[20].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#14 Warning LUT drives async reset alert LUT cell SFP_GEN[21].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#15 Warning LUT drives async reset alert LUT cell SFP_GEN[22].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#16 Warning LUT drives async reset alert LUT cell SFP_GEN[23].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#17 Warning LUT drives async reset alert LUT cell SFP_GEN[24].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#18 Warning LUT drives async reset alert LUT cell SFP_GEN[25].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#19 Warning LUT drives async reset alert LUT cell SFP_GEN[26].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#20 Warning LUT drives async reset alert LUT cell SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#21 Warning LUT drives async reset alert LUT cell SFP_GEN[28].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#22 Warning LUT drives async reset alert LUT cell SFP_GEN[29].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#23 Warning LUT drives async reset alert LUT cell SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#24 Warning LUT drives async reset alert LUT cell SFP_GEN[30].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#25 Warning LUT drives async reset alert LUT cell SFP_GEN[31].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#26 Warning LUT drives async reset alert LUT cell SFP_GEN[32].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#27 Warning LUT drives async reset alert LUT cell SFP_GEN[33].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#28 Warning LUT drives async reset alert LUT cell SFP_GEN[34].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#29 Warning LUT drives async reset alert LUT cell SFP_GEN[35].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#30 Warning LUT drives async reset alert LUT cell SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#31 Warning LUT drives async reset alert LUT cell SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#32 Warning LUT drives async reset alert LUT cell SFP_GEN[38].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#33 Warning LUT drives async reset alert LUT cell SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#34 Warning LUT drives async reset alert LUT cell SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#35 Warning LUT drives async reset alert LUT cell SFP_GEN[40].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#36 Warning LUT drives async reset alert LUT cell SFP_GEN[41].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#37 Warning LUT drives async reset alert LUT cell SFP_GEN[42].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#38 Warning LUT drives async reset alert LUT cell SFP_GEN[43].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#39 Warning LUT drives async reset alert LUT cell SFP_GEN[44].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#40 Warning LUT drives async reset alert LUT cell SFP_GEN[45].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#41 Warning LUT drives async reset alert LUT cell SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#42 Warning LUT drives async reset alert LUT cell SFP_GEN[47].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#43 Warning LUT drives async reset alert LUT cell SFP_GEN[4].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#44 Warning LUT drives async reset alert LUT cell SFP_GEN[5].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#45 Warning LUT drives async reset alert LUT cell SFP_GEN[6].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#46 Warning LUT drives async reset alert LUT cell SFP_GEN[7].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#47 Warning LUT drives async reset alert LUT cell SFP_GEN[8].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#48 Warning LUT drives async reset alert LUT cell SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#49 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#50 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#51 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#52 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#53 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#54 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#55 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#56 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#57 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#58 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#59 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#60 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#61 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#62 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#63 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#64 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#65 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#66 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#67 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#68 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#69 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#70 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#71 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#72 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#73 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#74 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#75 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#76 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#77 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#78 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#79 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#80 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#81 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#82 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#83 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#84 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#85 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#86 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#87 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#88 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#89 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#90 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#91 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#92 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#93 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#94 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#95 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#96 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#97 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/resetOnEven_gen.resetDurationCnter_s[3]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.resetDurationCnter_s_reg[0]/CLR, i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.resetDurationCnter_s_reg[1]/CLR, i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.resetDurationCnter_s_reg[2]/CLR, i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.resetDurationCnter_s_reg[3]/CLR, i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.rst_rstoneven_o_reg/CLR i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.sta_headerLocked_async_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#98 Warning LUT drives async reset alert LUT cell ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#99 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#100 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#101 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#102 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#103 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#104 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#105 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#106 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#107 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#108 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#109 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#110 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#111 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#112 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#113 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#114 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#115 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#116 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#117 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#118 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#119 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#120 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#121 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#122 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#123 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#124 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#125 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#126 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#127 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#128 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#129 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#130 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#131 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#132 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#133 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#134 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#135 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#136 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#137 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#138 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#139 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#140 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#141 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#142 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#143 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#144 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#145 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#146 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#147 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#148 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#149 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#150 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#151 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#152 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#153 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#154 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#155 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#156 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#157 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#158 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#159 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#160 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#161 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#162 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#163 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#164 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#165 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#166 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#167 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#168 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#169 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#170 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#171 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#172 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#173 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#174 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#175 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#176 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#177 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#178 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#179 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#180 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#181 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#182 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#183 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#184 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#185 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#186 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#187 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#188 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#189 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#190 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#191 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#192 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#193 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#194 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#195 Warning LUT drives async reset alert LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#196 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_i_1__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#197 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_i_1__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#198 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#199 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_i_1__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#200 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_i_1__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#201 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#202 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_i_1__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#203 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_i_1__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#204 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#205 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#206 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#207 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#208 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#209 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#210 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#211 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#212 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#213 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#214 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#215 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_i_1__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#216 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#217 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_i_1__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#218 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_i_1__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#219 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#220 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#221 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#222 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#223 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#224 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#225 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#226 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#227 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#228 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#229 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#230 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#231 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#232 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#233 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_i_1__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#234 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_i_1__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#235 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#236 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_i_1__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#237 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_i_1__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#238 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#239 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_i_1__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#240 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_i_1__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#241 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#242 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#243 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_i_1__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#244 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#245 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#246 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#247 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#248 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#249 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#250 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#251 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#252 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#253 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#254 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#255 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#256 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#257 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#258 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#259 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#260 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#261 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#262 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#263 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#264 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#265 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#266 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#267 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#268 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#269 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#270 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#271 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#272 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#273 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#274 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#275 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#276 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#277 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#278 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#279 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#280 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#281 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#282 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#283 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#284 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#285 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#286 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#287 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#288 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#289 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#290 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#291 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#292 Warning LUT drives async reset alert LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#293 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_i_1__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#294 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_i_1__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#295 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#296 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_i_1__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#297 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_i_1__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#298 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#299 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_i_1__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#300 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_i_1__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#301 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#302 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#303 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#304 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#305 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#306 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#307 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#308 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#309 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#310 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#311 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#312 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_i_1__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#313 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#314 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_i_1__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#315 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_i_1__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#316 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#317 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#318 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#319 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#320 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#321 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#322 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#323 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#324 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#325 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#326 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#327 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#328 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#329 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#330 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_i_1__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#331 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_i_1__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#332 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#333 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_i_1__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#334 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_i_1__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#335 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#336 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_i_1__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#337 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_i_1__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#338 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#339 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#340 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_i_1__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#341 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#342 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#343 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#344 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#345 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#346 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#347 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#348 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#349 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#350 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#351 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#352 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#353 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#354 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#355 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#356 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#357 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#358 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#359 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#360 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#361 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#362 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#363 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#364 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#365 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#366 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#367 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#368 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#369 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#370 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#371 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#372 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#373 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#374 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#375 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#376 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#377 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#378 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#379 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#380 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#381 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#382 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#383 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#384 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#385 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#386 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#387 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#388 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#389 Warning LUT drives async reset alert LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#390 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_i_1__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#391 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_i_1__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#392 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#393 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_i_1__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#394 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_i_1__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#395 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#396 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_i_1__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#397 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_i_1__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#398 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#399 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#400 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#401 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#402 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#403 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#404 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#405 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#406 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#407 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#408 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#409 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_i_1__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#410 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#411 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_i_1__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#412 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_i_1__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#413 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#414 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#415 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#416 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#417 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#418 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#419 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#420 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#421 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#422 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#423 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#424 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#425 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#426 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#427 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_i_1__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#428 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_i_1__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#429 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#430 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_i_1__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#431 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_i_1__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#432 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#433 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_i_1__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#434 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_i_1__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#435 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#436 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#437 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_i_1__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#438 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#439 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#440 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#441 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#442 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#443 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#444 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#445 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#446 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#447 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#448 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#449 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#450 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#451 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#452 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#453 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#454 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#455 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#456 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#457 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#458 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#459 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#460 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#461 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#462 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#463 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#464 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#465 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#466 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#467 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#468 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#469 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#470 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#471 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#472 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#473 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#474 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#475 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#476 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#477 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#478 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#479 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#480 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#481 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#482 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#483 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#484 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#485 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#486 Warning LUT drives async reset alert LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#487 Warning LUT drives async reset alert LUT cell i_axi_slave/generalRstProcess.timer[0]_i_3__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CLR (the first 15 of 324 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#488 Warning LUT drives async reset alert LUT cell i_axi_slave/generalRstProcess.timer[0]_i_3__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CLR (the first 15 of 324 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#489 Warning LUT drives async reset alert LUT cell i_axi_slave/generalRstProcess.timer[0]_i_3__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CLR (the first 15 of 324 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#490 Warning LUT drives async reset alert LUT cell i_axi_slave/generalRstProcess.timer[0]_i_3__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CLR (the first 15 of 324 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#491 Warning LUT drives async reset alert LUT cell i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#492 Warning LUT drives async reset alert LUT cell i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#493 Warning LUT drives async reset alert LUT cell i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_meta_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_meta_reg/PRE, i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_out_reg/PRE, i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_sync1_reg/PRE, i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_sync2_reg/PRE i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#494 Warning LUT drives async reset alert LUT cell i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#495 Warning LUT drives async reset alert LUT cell i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_sync2_reg/PRE i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#496 Warning LUT drives async reset alert LUT cell i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync2_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync3_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_sync2_reg/PRE i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: SYNTH-11#1 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#2 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#3 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#4 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#5 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#6 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#7 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#8 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#9 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#10 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#11 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#12 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#13 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#14 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#15 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#16 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#17 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#18 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#19 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#20 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#21 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#22 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#23 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#24 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#25 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#26 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#27 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#28 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#29 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#30 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#31 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#32 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#33 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#34 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#35 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#36 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#37 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#38 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#39 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#40 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#41 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#42 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#43 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#44 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#45 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#46 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#47 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#48 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#49 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#50 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#51 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#52 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#53 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#54 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#55 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#56 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#57 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#58 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#59 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#60 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#61 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#62 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#63 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[0].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#64 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#65 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#66 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#67 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[1].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#68 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#69 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#70 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[2].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#71 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#72 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#73 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#74 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[3].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#75 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#76 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#77 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#78 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[4].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#79 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#80 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#81 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#82 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[5].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#83 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#84 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#85 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#86 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[6].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#87 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#88 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#89 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#90 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_MUX_rate_k[7].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#91 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#92 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#93 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#94 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#95 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#96 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#97 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#98 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#99 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#100 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#101 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#102 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#103 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#104 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#105 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#106 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#107 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#108 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#109 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#110 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#111 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#112 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#113 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#114 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#115 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#116 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#117 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#118 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#119 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#120 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#121 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#122 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#123 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#124 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#125 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#126 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#127 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#128 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#129 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#130 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#131 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#132 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#133 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#134 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#135 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#136 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#137 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#138 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#139 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#140 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#141 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#142 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#143 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#144 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#145 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#146 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#147 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#148 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#149 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#150 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#151 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#152 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#153 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#154 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#155 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#156 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#157 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#158 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#159 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#160 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#161 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#162 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#163 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#164 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#165 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#166 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#167 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#168 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#169 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#170 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#171 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#172 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#173 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#174 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#175 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#176 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#177 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#178 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#179 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#180 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#181 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#182 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#183 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#184 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#185 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#186 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#187 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#188 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#189 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#190 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#191 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#192 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#193 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#194 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#195 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#196 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#197 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#198 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#199 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#200 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#201 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#202 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#203 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#204 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#205 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#206 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#207 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#208 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#209 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#210 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#211 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#212 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#213 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#214 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#215 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#216 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#217 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-11#218 Warning DSP output not registered DSP instance stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Related violations: SYNTH-12#1 Warning DSP input not registered DSP instance g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#2 Warning DSP input not registered DSP instance g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#3 Warning DSP input not registered DSP instance g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#4 Warning DSP input not registered DSP instance g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#5 Warning DSP input not registered DSP instance g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#6 Warning DSP input not registered DSP instance g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#7 Warning DSP input not registered DSP instance g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#8 Warning DSP input not registered DSP instance g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#9 Warning DSP input not registered DSP instance g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#10 Warning DSP input not registered DSP instance g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#11 Warning DSP input not registered DSP instance g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#12 Warning DSP input not registered DSP instance g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#13 Warning DSP input not registered DSP instance g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#14 Warning DSP input not registered DSP instance g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#15 Warning DSP input not registered DSP instance g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#16 Warning DSP input not registered DSP instance g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#17 Warning DSP input not registered DSP instance g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#18 Warning DSP input not registered DSP instance g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#19 Warning DSP input not registered DSP instance g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#20 Warning DSP input not registered DSP instance g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#21 Warning DSP input not registered DSP instance g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#22 Warning DSP input not registered DSP instance g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#23 Warning DSP input not registered DSP instance g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#24 Warning DSP input not registered DSP instance g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#25 Warning DSP input not registered DSP instance g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#26 Warning DSP input not registered DSP instance g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#27 Warning DSP input not registered DSP instance g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#28 Warning DSP input not registered DSP instance g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#29 Warning DSP input not registered DSP instance g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#30 Warning DSP input not registered DSP instance g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#31 Warning DSP input not registered DSP instance g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#32 Warning DSP input not registered DSP instance g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#33 Warning DSP input not registered DSP instance g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#34 Warning DSP input not registered DSP instance g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#35 Warning DSP input not registered DSP instance g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#36 Warning DSP input not registered DSP instance g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#37 Warning DSP input not registered DSP instance g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#38 Warning DSP input not registered DSP instance g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#39 Warning DSP input not registered DSP instance g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#40 Warning DSP input not registered DSP instance g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#41 Warning DSP input not registered DSP instance g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#42 Warning DSP input not registered DSP instance g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#43 Warning DSP input not registered DSP instance g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#44 Warning DSP input not registered DSP instance g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#45 Warning DSP input not registered DSP instance g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#46 Warning DSP input not registered DSP instance g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#47 Warning DSP input not registered DSP instance g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#48 Warning DSP input not registered DSP instance g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#49 Warning DSP input not registered DSP instance g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#50 Warning DSP input not registered DSP instance g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#51 Warning DSP input not registered DSP instance g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#52 Warning DSP input not registered DSP instance g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#53 Warning DSP input not registered DSP instance g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#54 Warning DSP input not registered DSP instance g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#55 Warning DSP input not registered DSP instance g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#56 Warning DSP input not registered DSP instance g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#57 Warning DSP input not registered DSP instance g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#58 Warning DSP input not registered DSP instance g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#59 Warning DSP input not registered DSP instance g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#60 Warning DSP input not registered DSP instance g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#61 Warning DSP input not registered DSP instance g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#62 Warning DSP input not registered DSP instance g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#63 Warning DSP input not registered DSP instance g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#64 Warning DSP input not registered DSP instance g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#65 Warning DSP input not registered DSP instance g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#66 Warning DSP input not registered DSP instance g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#67 Warning DSP input not registered DSP instance g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#68 Warning DSP input not registered DSP instance g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#69 Warning DSP input not registered DSP instance g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#70 Warning DSP input not registered DSP instance g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#71 Warning DSP input not registered DSP instance g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#72 Warning DSP input not registered DSP instance g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#73 Warning DSP input not registered DSP instance g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#74 Warning DSP input not registered DSP instance g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#75 Warning DSP input not registered DSP instance g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#76 Warning DSP input not registered DSP instance g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#77 Warning DSP input not registered DSP instance g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#78 Warning DSP input not registered DSP instance g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#79 Warning DSP input not registered DSP instance g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#80 Warning DSP input not registered DSP instance g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#81 Warning DSP input not registered DSP instance g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#82 Warning DSP input not registered DSP instance g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#83 Warning DSP input not registered DSP instance g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#84 Warning DSP input not registered DSP instance g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#85 Warning DSP input not registered DSP instance g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#86 Warning DSP input not registered DSP instance g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#87 Warning DSP input not registered DSP instance g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#88 Warning DSP input not registered DSP instance g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#89 Warning DSP input not registered DSP instance g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#90 Warning DSP input not registered DSP instance g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#91 Warning DSP input not registered DSP instance g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#92 Warning DSP input not registered DSP instance g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#93 Warning DSP input not registered DSP instance g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#94 Warning DSP input not registered DSP instance g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#95 Warning DSP input not registered DSP instance g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#96 Warning DSP input not registered DSP instance g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#97 Warning DSP input not registered DSP instance g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#98 Warning DSP input not registered DSP instance g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#99 Warning DSP input not registered DSP instance g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#100 Warning DSP input not registered DSP instance g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#101 Warning DSP input not registered DSP instance g_clock_rate_din[32].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#102 Warning DSP input not registered DSP instance g_clock_rate_din[32].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#103 Warning DSP input not registered DSP instance g_clock_rate_din[32].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#104 Warning DSP input not registered DSP instance g_clock_rate_din[32].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#105 Warning DSP input not registered DSP instance g_clock_rate_din[33].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#106 Warning DSP input not registered DSP instance g_clock_rate_din[33].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#107 Warning DSP input not registered DSP instance g_clock_rate_din[33].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#108 Warning DSP input not registered DSP instance g_clock_rate_din[33].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#109 Warning DSP input not registered DSP instance g_clock_rate_din[34].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#110 Warning DSP input not registered DSP instance g_clock_rate_din[34].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#111 Warning DSP input not registered DSP instance g_clock_rate_din[34].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#112 Warning DSP input not registered DSP instance g_clock_rate_din[34].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#113 Warning DSP input not registered DSP instance g_clock_rate_din[35].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#114 Warning DSP input not registered DSP instance g_clock_rate_din[35].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#115 Warning DSP input not registered DSP instance g_clock_rate_din[35].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#116 Warning DSP input not registered DSP instance g_clock_rate_din[35].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#117 Warning DSP input not registered DSP instance g_clock_rate_din[36].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#118 Warning DSP input not registered DSP instance g_clock_rate_din[36].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#119 Warning DSP input not registered DSP instance g_clock_rate_din[36].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#120 Warning DSP input not registered DSP instance g_clock_rate_din[36].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#121 Warning DSP input not registered DSP instance g_clock_rate_din[37].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#122 Warning DSP input not registered DSP instance g_clock_rate_din[37].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#123 Warning DSP input not registered DSP instance g_clock_rate_din[37].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#124 Warning DSP input not registered DSP instance g_clock_rate_din[37].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#125 Warning DSP input not registered DSP instance g_clock_rate_din[38].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#126 Warning DSP input not registered DSP instance g_clock_rate_din[38].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#127 Warning DSP input not registered DSP instance g_clock_rate_din[38].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#128 Warning DSP input not registered DSP instance g_clock_rate_din[38].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#129 Warning DSP input not registered DSP instance g_clock_rate_din[39].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#130 Warning DSP input not registered DSP instance g_clock_rate_din[39].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#131 Warning DSP input not registered DSP instance g_clock_rate_din[39].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#132 Warning DSP input not registered DSP instance g_clock_rate_din[39].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#133 Warning DSP input not registered DSP instance g_clock_rate_din[3].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#134 Warning DSP input not registered DSP instance g_clock_rate_din[3].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#135 Warning DSP input not registered DSP instance g_clock_rate_din[3].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#136 Warning DSP input not registered DSP instance g_clock_rate_din[3].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#137 Warning DSP input not registered DSP instance g_clock_rate_din[40].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#138 Warning DSP input not registered DSP instance g_clock_rate_din[40].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#139 Warning DSP input not registered DSP instance g_clock_rate_din[40].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#140 Warning DSP input not registered DSP instance g_clock_rate_din[40].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#141 Warning DSP input not registered DSP instance g_clock_rate_din[41].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#142 Warning DSP input not registered DSP instance g_clock_rate_din[41].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#143 Warning DSP input not registered DSP instance g_clock_rate_din[41].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#144 Warning DSP input not registered DSP instance g_clock_rate_din[41].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#145 Warning DSP input not registered DSP instance g_clock_rate_din[42].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#146 Warning DSP input not registered DSP instance g_clock_rate_din[42].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#147 Warning DSP input not registered DSP instance g_clock_rate_din[42].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#148 Warning DSP input not registered DSP instance g_clock_rate_din[42].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#149 Warning DSP input not registered DSP instance g_clock_rate_din[43].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#150 Warning DSP input not registered DSP instance g_clock_rate_din[43].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#151 Warning DSP input not registered DSP instance g_clock_rate_din[43].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#152 Warning DSP input not registered DSP instance g_clock_rate_din[43].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#153 Warning DSP input not registered DSP instance g_clock_rate_din[44].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#154 Warning DSP input not registered DSP instance g_clock_rate_din[44].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#155 Warning DSP input not registered DSP instance g_clock_rate_din[44].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#156 Warning DSP input not registered DSP instance g_clock_rate_din[44].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#157 Warning DSP input not registered DSP instance g_clock_rate_din[45].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#158 Warning DSP input not registered DSP instance g_clock_rate_din[45].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#159 Warning DSP input not registered DSP instance g_clock_rate_din[45].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#160 Warning DSP input not registered DSP instance g_clock_rate_din[45].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#161 Warning DSP input not registered DSP instance g_clock_rate_din[46].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#162 Warning DSP input not registered DSP instance g_clock_rate_din[46].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#163 Warning DSP input not registered DSP instance g_clock_rate_din[46].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#164 Warning DSP input not registered DSP instance g_clock_rate_din[46].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#165 Warning DSP input not registered DSP instance g_clock_rate_din[47].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#166 Warning DSP input not registered DSP instance g_clock_rate_din[47].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#167 Warning DSP input not registered DSP instance g_clock_rate_din[47].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#168 Warning DSP input not registered DSP instance g_clock_rate_din[47].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#169 Warning DSP input not registered DSP instance g_clock_rate_din[4].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#170 Warning DSP input not registered DSP instance g_clock_rate_din[4].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#171 Warning DSP input not registered DSP instance g_clock_rate_din[4].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#172 Warning DSP input not registered DSP instance g_clock_rate_din[4].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#173 Warning DSP input not registered DSP instance g_clock_rate_din[5].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#174 Warning DSP input not registered DSP instance g_clock_rate_din[5].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#175 Warning DSP input not registered DSP instance g_clock_rate_din[5].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#176 Warning DSP input not registered DSP instance g_clock_rate_din[5].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#177 Warning DSP input not registered DSP instance g_clock_rate_din[6].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#178 Warning DSP input not registered DSP instance g_clock_rate_din[6].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#179 Warning DSP input not registered DSP instance g_clock_rate_din[6].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#180 Warning DSP input not registered DSP instance g_clock_rate_din[6].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#181 Warning DSP input not registered DSP instance g_clock_rate_din[7].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#182 Warning DSP input not registered DSP instance g_clock_rate_din[7].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#183 Warning DSP input not registered DSP instance g_clock_rate_din[7].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#184 Warning DSP input not registered DSP instance g_clock_rate_din[7].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#185 Warning DSP input not registered DSP instance g_clock_rate_din[8].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#186 Warning DSP input not registered DSP instance g_clock_rate_din[8].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#187 Warning DSP input not registered DSP instance g_clock_rate_din[8].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#188 Warning DSP input not registered DSP instance g_clock_rate_din[8].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#189 Warning DSP input not registered DSP instance g_clock_rate_din[9].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#190 Warning DSP input not registered DSP instance g_clock_rate_din[9].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#191 Warning DSP input not registered DSP instance g_clock_rate_din[9].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#192 Warning DSP input not registered DSP instance g_clock_rate_din[9].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#193 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#194 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#195 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#196 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#197 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#198 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#199 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#200 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#201 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#202 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#203 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#204 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#205 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#206 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#207 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#208 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#209 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#210 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#211 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#212 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#213 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#214 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#215 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#216 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#217 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#218 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#219 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#220 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#221 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#222 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#223 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#224 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#225 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#226 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#227 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#228 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#229 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#230 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#231 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#232 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#233 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#234 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#235 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#236 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#237 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#238 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#239 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#240 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#241 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#242 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#243 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#244 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#245 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#246 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#247 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#248 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#249 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#250 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#251 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#252 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#253 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#254 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#255 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#256 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#257 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#258 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#259 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#260 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#261 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#262 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#263 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#264 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#265 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#266 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#267 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#268 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#269 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#270 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#271 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#272 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#273 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#274 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#275 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#276 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#277 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#278 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#279 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#280 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#281 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#282 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#283 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#284 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#285 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#286 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#287 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#288 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#289 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#290 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#291 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#292 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#293 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#294 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#295 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#296 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#297 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#298 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#299 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#300 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#301 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#302 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#303 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#304 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#305 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#306 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#307 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#308 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#309 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#310 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#311 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#312 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#313 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#314 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#315 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#316 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#317 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#318 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#319 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#320 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#321 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#322 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[10].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#323 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[11].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#324 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[12].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#325 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[13].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#326 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[14].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#327 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[15].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#328 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[16].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#329 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[17].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#330 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[18].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#331 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[19].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#332 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#333 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[20].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#334 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[21].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#335 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[22].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#336 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[23].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#337 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[24].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#338 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[25].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#339 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[26].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#340 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[27].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#341 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[28].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#342 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[29].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#343 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[2].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#344 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[30].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#345 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[31].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#346 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[32].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#347 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[33].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#348 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[34].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#349 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[35].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#350 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[36].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#351 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[37].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#352 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[38].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#353 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[39].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#354 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[3].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#355 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[40].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#356 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[41].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#357 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[42].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#358 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[43].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#359 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[44].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#360 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[45].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#361 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[46].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#362 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[47].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#363 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[48].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#364 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#365 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[4].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#366 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#367 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[51].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#368 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[52].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#369 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[53].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#370 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[54].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#371 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[55].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#372 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[56].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#373 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[57].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#374 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[58].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#375 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[59].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#376 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[5].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#377 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[60].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#378 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[61].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#379 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[62].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#380 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[63].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#381 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[6].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#382 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[7].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#383 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[8].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-12#384 Warning DSP input not registered DSP instance stat_regs_inst/g_DSP_rate[9].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Related violations: SYNTH-13#1 Warning combinational multiplier Detected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst. Related violations: SYNTH-13#2 Warning combinational multiplier Detected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst. Related violations: SYNTH-13#3 Warning combinational multiplier Detected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst. Related violations: SYNTH-13#4 Warning combinational multiplier Detected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst. Related violations: SYNTH-13#5 Warning combinational multiplier Detected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst. Related violations: SYNTH-13#6 Warning combinational multiplier Detected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst. Related violations: SYNTH-13#7 Warning combinational multiplier Detected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst. Related violations: SYNTH-13#8 Warning combinational multiplier Detected combinational multiplier in DSP instance stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst. Related violations: SYNTH-13#9 Warning combinational multiplier Detected combinational multiplier in DSP instance stat_regs_inst/i_DSP_cntr. Related violations: TIMING-9#1 Warning Unknown CDC Logic One or more asynchronous Clock Domain Crossing has been detected between 2 clock domains through a set_false_path or a set_clock_groups or set_max_delay -datapath_only constraint but no double-registers logic synchronizer has been found on the side of the capture clock. It is recommended to run report_cdc for a complete and detailed CDC coverage. Please consider using XPM_CDC to avoid Critical severities Related violations: TIMING-10#1 Warning Missing property on synchronizer One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage Related violations: TIMING-18#1 Warning Missing input or output delay An input delay is missing on FF_RX_PRESENTn[0] relative to clock(s) ipb_clk Related violations: TIMING-18#2 Warning Missing input or output delay An input delay is missing on FF_RX_PRESENTn[1] relative to clock(s) ipb_clk Related violations: TIMING-18#3 Warning Missing input or output delay An input delay is missing on FF_RX_PRESENTn[2] relative to clock(s) ipb_clk Related violations: TIMING-18#4 Warning Missing input or output delay An input delay is missing on FF_RX_PRESENTn[3] relative to clock(s) ipb_clk Related violations: TIMING-18#5 Warning Missing input or output delay An input delay is missing on FF_RX_SCL[0] relative to clock(s) ipb_clk Related violations: TIMING-18#6 Warning Missing input or output delay An input delay is missing on FF_RX_SCL[1] relative to clock(s) ipb_clk Related violations: TIMING-18#7 Warning Missing input or output delay An input delay is missing on FF_RX_SCL[2] relative to clock(s) ipb_clk Related violations: TIMING-18#8 Warning Missing input or output delay An input delay is missing on FF_RX_SCL[3] relative to clock(s) ipb_clk Related violations: TIMING-18#9 Warning Missing input or output delay An input delay is missing on FF_RX_SDA[0] relative to clock(s) ipb_clk Related violations: TIMING-18#10 Warning Missing input or output delay An input delay is missing on FF_RX_SDA[1] relative to clock(s) ipb_clk Related violations: TIMING-18#11 Warning Missing input or output delay An input delay is missing on FF_RX_SDA[2] relative to clock(s) ipb_clk Related violations: TIMING-18#12 Warning Missing input or output delay An input delay is missing on FF_RX_SDA[3] relative to clock(s) ipb_clk Related violations: TIMING-18#13 Warning Missing input or output delay An input delay is missing on FF_TX_PRESENTn[0] relative to clock(s) ipb_clk Related violations: TIMING-18#14 Warning Missing input or output delay An input delay is missing on FF_TX_PRESENTn[1] relative to clock(s) ipb_clk Related violations: TIMING-18#15 Warning Missing input or output delay An input delay is missing on FF_TX_PRESENTn[2] relative to clock(s) ipb_clk Related violations: TIMING-18#16 Warning Missing input or output delay An input delay is missing on FF_TX_PRESENTn[3] relative to clock(s) ipb_clk Related violations: TIMING-18#17 Warning Missing input or output delay An input delay is missing on FF_TX_SCL[0] relative to clock(s) ipb_clk Related violations: TIMING-18#18 Warning Missing input or output delay An input delay is missing on FF_TX_SCL[1] relative to clock(s) ipb_clk Related violations: TIMING-18#19 Warning Missing input or output delay An input delay is missing on FF_TX_SCL[2] relative to clock(s) ipb_clk Related violations: TIMING-18#20 Warning Missing input or output delay An input delay is missing on FF_TX_SCL[3] relative to clock(s) ipb_clk Related violations: TIMING-18#21 Warning Missing input or output delay An input delay is missing on FF_TX_SDA[0] relative to clock(s) ipb_clk Related violations: TIMING-18#22 Warning Missing input or output delay An input delay is missing on FF_TX_SDA[1] relative to clock(s) ipb_clk Related violations: TIMING-18#23 Warning Missing input or output delay An input delay is missing on FF_TX_SDA[2] relative to clock(s) ipb_clk Related violations: TIMING-18#24 Warning Missing input or output delay An input delay is missing on FF_TX_SDA[3] relative to clock(s) ipb_clk Related violations: TIMING-18#25 Warning Missing input or output delay An input delay is missing on Si_LOLb relative to clock(s) clk125, ipb_clk Related violations: TIMING-18#26 Warning Missing input or output delay An input delay is missing on Si_SCL relative to clock(s) ipb_clk Related violations: TIMING-18#27 Warning Missing input or output delay An input delay is missing on Si_SDA relative to clock(s) ipb_clk Related violations: TIMING-18#28 Warning Missing input or output delay An input delay is missing on board_id[0] relative to clock(s) ipb_clk Related violations: TIMING-18#29 Warning Missing input or output delay An input delay is missing on board_id[1] relative to clock(s) ipb_clk Related violations: TIMING-18#30 Warning Missing input or output delay An input delay is missing on board_id[2] relative to clock(s) ipb_clk Related violations: TIMING-18#31 Warning Missing input or output delay An input delay is missing on board_id[3] relative to clock(s) ipb_clk Related violations: TIMING-18#32 Warning Missing input or output delay An input delay is missing on board_id[4] relative to clock(s) ipb_clk Related violations: TIMING-18#33 Warning Missing input or output delay An input delay is missing on board_id[5] relative to clock(s) ipb_clk Related violations: TIMING-18#34 Warning Missing input or output delay An input delay is missing on board_id[6] relative to clock(s) ipb_clk Related violations: TIMING-18#35 Warning Missing input or output delay An output delay is missing on FF_RX_RESETn[0] relative to clock(s) ipb_clk Related violations: TIMING-18#36 Warning Missing input or output delay An output delay is missing on FF_RX_RESETn[1] relative to clock(s) ipb_clk Related violations: TIMING-18#37 Warning Missing input or output delay An output delay is missing on FF_RX_RESETn[2] relative to clock(s) ipb_clk Related violations: TIMING-18#38 Warning Missing input or output delay An output delay is missing on FF_RX_RESETn[3] relative to clock(s) ipb_clk Related violations: TIMING-18#39 Warning Missing input or output delay An output delay is missing on FF_TX_RESETn[0] relative to clock(s) ipb_clk Related violations: TIMING-18#40 Warning Missing input or output delay An output delay is missing on FF_TX_RESETn[1] relative to clock(s) ipb_clk Related violations: TIMING-18#41 Warning Missing input or output delay An output delay is missing on FF_TX_RESETn[2] relative to clock(s) ipb_clk Related violations: TIMING-18#42 Warning Missing input or output delay An output delay is missing on FF_TX_RESETn[3] relative to clock(s) ipb_clk Related violations: TIMING-18#43 Warning Missing input or output delay An output delay is missing on Si_IN_SEL[0] relative to clock(s) ipb_clk Related violations: TIMING-18#44 Warning Missing input or output delay An output delay is missing on Si_IN_SEL[1] relative to clock(s) ipb_clk Related violations: TIMING-24#1 Warning Overridden Max delay datapath only An asynchronous set_clock_groups or a set_false path (see constraint position 671 in the Timing Constraints window in Vivado IDE) between clocks axi_c2c_phy_clk and clk125 overrides a set_max_delay -datapath_only (position 3). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#2 Warning Overridden Max delay datapath only An asynchronous set_clock_groups or a set_false path (see constraint position 671 in the Timing Constraints window in Vivado IDE) between clocks axi_c2c_phy_clk and clk125 overrides a set_max_delay -datapath_only (position 702). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#3 Warning Overridden Max delay datapath only An asynchronous set_clock_groups or a set_false path (see constraint position 671 in the Timing Constraints window in Vivado IDE) between clocks axi_c2c_phy_clk and clk125 overrides a set_max_delay -datapath_only (position 706). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#4 Warning Overridden Max delay datapath only An asynchronous set_clock_groups or a set_false path (see constraint position 671 in the Timing Constraints window in Vivado IDE) between clocks axi_c2c_phy_clk and clk125 overrides a set_max_delay -datapath_only (position 710). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#5 Warning Overridden Max delay datapath only An asynchronous set_clock_groups or a set_false path (see constraint position 671 in the Timing Constraints window in Vivado IDE) between clocks axi_c2c_phy_clk and clk125 overrides a set_max_delay -datapath_only (position 726). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#6 Warning Overridden Max delay datapath only An asynchronous set_clock_groups or a set_false path (see constraint position 671 in the Timing Constraints window in Vivado IDE) between clocks axi_c2c_phy_clk and clk125 overrides a set_max_delay -datapath_only (position 732). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#7 Warning Overridden Max delay datapath only An asynchronous set_clock_groups or a set_false path (see constraint position 671 in the Timing Constraints window in Vivado IDE) between clocks clk125 and axi_c2c_phy_clk overrides a set_max_delay -datapath_only (position 704). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#8 Warning Overridden Max delay datapath only An asynchronous set_clock_groups or a set_false path (see constraint position 671 in the Timing Constraints window in Vivado IDE) between clocks clk125 and axi_c2c_phy_clk overrides a set_max_delay -datapath_only (position 708). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#9 Warning Overridden Max delay datapath only An asynchronous set_clock_groups or a set_false path (see constraint position 671 in the Timing Constraints window in Vivado IDE) between clocks clk125 and axi_c2c_phy_clk overrides a set_max_delay -datapath_only (position 712). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#10 Warning Overridden Max delay datapath only An asynchronous set_clock_groups or a set_false path (see constraint position 671 in the Timing Constraints window in Vivado IDE) between clocks clk125 and axi_c2c_phy_clk overrides a set_max_delay -datapath_only (position 722). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#11 Warning Overridden Max delay datapath only An asynchronous set_clock_groups or a set_false path (see constraint position 671 in the Timing Constraints window in Vivado IDE) between clocks clk125 and axi_c2c_phy_clk overrides a set_max_delay -datapath_only (position 724). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-47#1 Warning False path or asynchronous clock group between synchronous clocks A Clock Group timing constraint is set between synchronous clocks TTC_rxusrclk and fabric_clk_in (see constraint position 668 in the Timing Constraint window in Vivado IDE). Masking entire synchronous clock domains via set_false_path or set_clock_groups may result in failure in hardware. Related violations: ULMTCS-1#1 Warning Control Sets use limits recommend reduction This design uses 20801 control sets (vs. available limit of 165840, determined by 1 control set per CLB). This exceeds the control set use guideline of 7.5 percent. This is at a level where reduction is RECOMMENDED (see UG949). Use report_control_sets to get more details. Related violations: XDCB-1#1 Warning Runtime intensive exceptions The following constraint contains more than 10000 objects. To preserve runtime and memory performance, it is recommended to include minimum number of objects. Check whether this list can be simplified. -from = expands to 10704 design objects. set_multicycle_path -hold -from [get_pins {*gbtbank/*/*gbt_rxgearbox_inst/*_reg[*]/C}] -to [get_pins *gbtbank/*/*/descrambler/*/*_reg*/D] 5 D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc (Line: 149) Related violations: XDCB-1#2 Warning Runtime intensive exceptions The following constraint contains more than 10000 objects. To preserve runtime and memory performance, it is recommended to include minimum number of objects. Check whether this list can be simplified. -from = expands to 10704 design objects. set_multicycle_path -setup -from [get_pins {*gbtbank/*/*gbt_rxgearbox_inst/*_reg[*]/C}] -to [get_pins *gbtbank/*/*/descrambler/*/*_reg*/D] 6 D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc (Line: 148) Related violations: CLKC-27#1 Advisory MMCME3 with BUF_IN drives sequential IO not with CLKOUT0 The MMCME3 cell i_clk125_MMCM has COMPENSATION value BUF_IN, but CLKOUT2 output drives sequential IO cells. (The problem cell is i_I2C_if/I2C_array[8].i2c_sda_inst/IBUFCTRL_INST (in i_I2C_if/I2C_array[8].i2c_sda_inst macro).) In order to achieve insertion delay and phase-alignment for the IO sequential cells, a COMPENSATION of ZHOLD must be used and CLKOUT0 output must be the driver%STR Related violations: CLKC-29#1 Advisory MMCME3 not driven by IO has BUFG in feedback loop The MMCME3 cell fabric_clk_MMCM has a BUFGCE CLKFBOUT_bufg clock buffer in the feedback loop, but the clock input is not directly driven by an I/O to create a Zero Delay Buffer Clock (a common use for having a buffer in the feedback loop). If there is no specific need for this buffer in the feedback loop (e.g. no timing paths between CLKINx/CLKOUTx domains or low latency requirement), then it is suggested to remove that BUFG* from the feedback path. This will allow for a lower power solution and free the clock resource for other purposes. Related violations: CLKC-29#2 Advisory MMCME3 not driven by IO has BUFG in feedback loop The MMCME3 cell i_clk125_MMCM has a BUFGCE i_clk125_bufg clock buffer in the feedback loop, but the clock input is not directly driven by an I/O to create a Zero Delay Buffer Clock (a common use for having a buffer in the feedback loop). If there is no specific need for this buffer in the feedback loop (e.g. no timing paths between CLKINx/CLKOUTx domains or low latency requirement), then it is suggested to remove that BUFG* from the feedback path. This will allow for a lower power solution and free the clock resource for other purposes. Related violations: CLKC-55#1 Advisory MMCME3 with global clock driver has no LOC The MMCME3_ADV cell fabric_clk_MMCM CLKIN1 or CLKIN2 pin is driven by global Clock buffer(s) i_tcds2_if/bufgce_clk_40_rx and does not have a LOC constraint. It is recommended to LOC the MMCM and use the CLOCK_DEDICATED_ROUTE constraint on the net(s) driven by the global Clock buffer(s). Related violations: CLKC-55#2 Advisory MMCME3 with global clock driver has no LOC The MMCME3_ADV cell i_clk125_MMCM CLKIN1 or CLKIN2 pin is driven by global Clock buffer(s) i_refclk125_bufg and does not have a LOC constraint. It is recommended to LOC the MMCM and use the CLOCK_DEDICATED_ROUTE constraint on the net(s) driven by the global Clock buffer(s). Related violations: