2016.3" PB_VioResultsD 1.2ngFEC_top_drc_opted.rpxh#px DRC ResultsWarning"CFGBVS-1*3Missing CFGBVS and CONFIG_VOLTAGE Design Properties2 CFGBVS-1#18BNeither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information.JNeither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information.Warning"DPIP-2*Input pipelining2DPIP-2#18BDSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2DPIP-2#28BDSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2DPIP-2#38BDSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2DPIP-2#48BDSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2DPIP-2#58BDSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2DPIP-2#68BDSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2DPIP-2#78BDSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2DPIP-2#88BDSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_inst Warning"DPIP-2*Input pipelining2DPIP-2#98BDSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#108BDSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#118BDSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#128BDSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#138BDSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#148BDSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#158BDSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#168BDSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#178BDSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#188BDSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#198BDSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#208BDSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#218BDSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#228BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#238BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#248BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#258BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#268BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#278BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#288BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#298BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#308BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#318BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#328BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_inst!Warning"DPIP-2*Input pipelining2 DPIP-2#338BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_inst"Warning"DPIP-2*Input pipelining2 DPIP-2#348BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_inst#Warning"DPIP-2*Input pipelining2 DPIP-2#358BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_inst$Warning"DPIP-2*Input pipelining2 DPIP-2#368BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_inst%Warning"DPIP-2*Input pipelining2 DPIP-2#378BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_inst&Warning"DPIP-2*Input pipelining2 DPIP-2#388BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_inst'Warning"DPIP-2*Input pipelining2 DPIP-2#398BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_inst(Warning"DPIP-2*Input pipelining2 DPIP-2#408BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_inst)Warning"DPIP-2*Input pipelining2 DPIP-2#418BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_inst*Warning"DPIP-2*Input pipelining2 DPIP-2#428BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_inst+Warning"DPIP-2*Input pipelining2 DPIP-2#438BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_inst,Warning"DPIP-2*Input pipelining2 DPIP-2#448BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_inst-Warning"DPIP-2*Input pipelining2 DPIP-2#458BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_inst.Warning"DPIP-2*Input pipelining2 DPIP-2#468BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Ï. DSP48E2_inst * +A Ï.* DSP48E2_inst/Warning"DPIP-2*Input pipelining2 DPIP-2#478BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Ï. DSP48E2_inst * +B Ï.* DSP48E2_inst0Warning"DPIP-2*Input pipelining2 DPIP-2#488BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Ï. DSP48E2_inst * C Ï.* DSP48E2_inst1Warning"DPIP-2*Input pipelining2 DPIP-2#498BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Ǐ. DSP48E2_inst * +A Ǐ.* DSP48E2_inst2Warning"DPIP-2*Input pipelining2 DPIP-2#508BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Ǐ. DSP48E2_inst * +B Ǐ.* DSP48E2_inst3Warning"DPIP-2*Input pipelining2 DPIP-2#518BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Ǐ. DSP48E2_inst * C Ǐ.* DSP48E2_inst4Warning"DPIP-2*Input pipelining2 DPIP-2#528BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ˏ. DSP48E2_inst * +A ˏ.* DSP48E2_inst5Warning"DPIP-2*Input pipelining2 DPIP-2#538BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ˏ. DSP48E2_inst * +B ˏ.* DSP48E2_inst6Warning"DPIP-2*Input pipelining2 DPIP-2#548BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ˏ. DSP48E2_inst * C ˏ.* DSP48E2_inst7Warning"DPIP-2*Input pipelining2 DPIP-2#558BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Ϗ. DSP48E2_inst * +A Ϗ.* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#568BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Ϗ. DSP48E2_inst * +B Ϗ.* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#578BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Ϗ. DSP48E2_inst * C Ϗ.* DSP48E2_inst:Warning"DPIP-2*Input pipelining2 DPIP-2#588BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ӏ. DSP48E2_inst * +A ӏ.* DSP48E2_inst;Warning"DPIP-2*Input pipelining2 DPIP-2#598BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ӏ. DSP48E2_inst * +B ӏ.* DSP48E2_inst<Warning"DPIP-2*Input pipelining2 DPIP-2#608BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ӏ. DSP48E2_inst * C ӏ.* DSP48E2_inst=Warning"DPIP-2*Input pipelining2 DPIP-2#618BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ׏. DSP48E2_inst * +A ׏.* DSP48E2_inst>Warning"DPIP-2*Input pipelining2 DPIP-2#628BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ׏. DSP48E2_inst * +B ׏.* DSP48E2_inst?Warning"DPIP-2*Input pipelining2 DPIP-2#638BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ׏. DSP48E2_inst * C ׏.* DSP48E2_inst@Warning"DPIP-2*Input pipelining2 DPIP-2#648BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ۏ. DSP48E2_inst * +A ۏ.* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#658BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ۏ. DSP48E2_inst * +B ۏ.* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#668BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ۏ. DSP48E2_inst * C ۏ.* DSP48E2_instCWarning"DPIP-2*Input pipelining2 DPIP-2#678BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ߏ. DSP48E2_inst * +A ߏ.* DSP48E2_instDWarning"DPIP-2*Input pipelining2 DPIP-2#688BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ߏ. DSP48E2_inst * +B ߏ.* DSP48E2_instEWarning"DPIP-2*Input pipelining2 DPIP-2#698BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ߏ. DSP48E2_inst * C ߏ.* DSP48E2_instFWarning"DPIP-2*Input pipelining2 DPIP-2#708BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instGWarning"DPIP-2*Input pipelining2 DPIP-2#718BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instHWarning"DPIP-2*Input pipelining2 DPIP-2#728BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instIWarning"DPIP-2*Input pipelining2 DPIP-2#738BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instJWarning"DPIP-2*Input pipelining2 DPIP-2#748BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instKWarning"DPIP-2*Input pipelining2 DPIP-2#758BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instLWarning"DPIP-2*Input pipelining2 DPIP-2#768BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instMWarning"DPIP-2*Input pipelining2 DPIP-2#778BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instNWarning"DPIP-2*Input pipelining2 DPIP-2#788BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instOWarning"DPIP-2*Input pipelining2 DPIP-2#798BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instPWarning"DPIP-2*Input pipelining2 DPIP-2#808BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instQWarning"DPIP-2*Input pipelining2 DPIP-2#818BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instRWarning"DPIP-2*Input pipelining2 DPIP-2#828BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instSWarning"DPIP-2*Input pipelining2 DPIP-2#838BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instTWarning"DPIP-2*Input pipelining2 DPIP-2#848BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instUWarning"DPIP-2*Input pipelining2 DPIP-2#858BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instVWarning"DPIP-2*Input pipelining2 DPIP-2#868BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWWarning"DPIP-2*Input pipelining2 DPIP-2#878BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instXWarning"DPIP-2*Input pipelining2 DPIP-2#888BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instYWarning"DPIP-2*Input pipelining2 DPIP-2#898BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instZWarning"DPIP-2*Input pipelining2 DPIP-2#908BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_inst[Warning"DPIP-2*Input pipelining2 DPIP-2#918BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_inst\Warning"DPIP-2*Input pipelining2 DPIP-2#928BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_inst]Warning"DPIP-2*Input pipelining2 DPIP-2#938BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_inst^Warning"DPIP-2*Input pipelining2 DPIP-2#948BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_inst_Warning"DPIP-2*Input pipelining2 DPIP-2#958BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_inst`Warning"DPIP-2*Input pipelining2 DPIP-2#968BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instaWarning"DPIP-2*Input pipelining2 DPIP-2#978BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instbWarning"DPIP-2*Input pipelining2 DPIP-2#988BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instcWarning"DPIP-2*Input pipelining2 DPIP-2#998BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instdWarning"DPIP-2*Input pipelining2 DPIP-2#1008BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_insteWarning"DPIP-2*Input pipelining2 DPIP-2#1018BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instfWarning"DPIP-2*Input pipelining2 DPIP-2#1028BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instgWarning"DPIP-2*Input pipelining2 DPIP-2#1038BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_insthWarning"DPIP-2*Input pipelining2 DPIP-2#1048BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instiWarning"DPIP-2*Input pipelining2 DPIP-2#1058BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instjWarning"DPIP-2*Input pipelining2 DPIP-2#1068BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instkWarning"DPIP-2*Input pipelining2 DPIP-2#1078BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instlWarning"DPIP-2*Input pipelining2 DPIP-2#1088BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instmWarning"DPIP-2*Input pipelining2 DPIP-2#1098BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instnWarning"DPIP-2*Input pipelining2 DPIP-2#1108BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instoWarning"DPIP-2*Input pipelining2 DPIP-2#1118BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instpWarning"DPIP-2*Input pipelining2 DPIP-2#1128BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instqWarning"DPIP-2*Input pipelining2 DPIP-2#1138BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instrWarning"DPIP-2*Input pipelining2 DPIP-2#1148BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instsWarning"DPIP-2*Input pipelining2 DPIP-2#1158BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_insttWarning"DPIP-2*Input pipelining2 DPIP-2#1168BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instuWarning"DPIP-2*Input pipelining2 DPIP-2#1178BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instvWarning"DPIP-2*Input pipelining2 DPIP-2#1188BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instwWarning"DPIP-2*Input pipelining2 DPIP-2#1198BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instxWarning"DPIP-2*Input pipelining2 DPIP-2#1208BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#1218BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#1228BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_inst{Warning"DPIP-2*Input pipelining2 DPIP-2#1238BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_inst|Warning"DPIP-2*Input pipelining2 DPIP-2#1248BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_inst}Warning"DPIP-2*Input pipelining2 DPIP-2#1258BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_inst~Warning"DPIP-2*Input pipelining2 DPIP-2#1268BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1278BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1288BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1298BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1308BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1318BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1328BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1338BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1348BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1358BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1368BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1378BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1388BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1398BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1408BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1418BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1428BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Ð. DSP48E2_inst * +A Ð.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1438BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Ð. DSP48E2_inst * +B Ð.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1448BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Ð. DSP48E2_inst * C Ð.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1458BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ǐ. DSP48E2_inst * +A ǐ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1468BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ǐ. DSP48E2_inst * +B ǐ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1478BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ǐ. DSP48E2_inst * C ǐ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1488BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ː. DSP48E2_inst * +A ː.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1498BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ː. DSP48E2_inst * +B ː.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1508BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ː. DSP48E2_inst * C ː.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1518BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ϐ. DSP48E2_inst * +A ϐ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1528BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ϐ. DSP48E2_inst * +B ϐ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1538BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ϐ. DSP48E2_inst * C ϐ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1548BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Ӑ. DSP48E2_inst * +A Ӑ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1558BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Ӑ. DSP48E2_inst * +B Ӑ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1568BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Ӑ. DSP48E2_inst * C Ӑ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1578BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. א. DSP48E2_inst * +A א.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1588BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. א. DSP48E2_inst * +B א.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1598BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. א. DSP48E2_inst * C א.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1608BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ې. DSP48E2_inst * +A ې.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1618BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ې. DSP48E2_inst * +B ې.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1628BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ې. DSP48E2_inst * C ې.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1638BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ߐ. DSP48E2_inst * +A ߐ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1648BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ߐ. DSP48E2_inst * +B ߐ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1658BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ߐ. DSP48E2_inst * C ߐ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1668BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1678BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1688BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1698BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1708BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1718BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1728BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1738BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1748BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1758BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1768BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1778BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1788BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1798BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1808BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1818BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1828BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1838BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1848BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1858BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1868BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1878BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1888BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1898BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1908BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1918BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1928BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1938BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1948BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1958BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1968BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1978BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1988BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#1998BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2008BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2018BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2028BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2038BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2048BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2058BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2068BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2078BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2088BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2098BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2108BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2118BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2128BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2138BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2148BDSP ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +A .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2158BDSP ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * +B .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2168BDSP ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2178BDSP g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2188BDSP g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Ñ. DSP48E2_inst * C Ñ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2198BDSP g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2208BDSP g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2218BDSP g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2228BDSP g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Д. DSP48E2_inst * C Д.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2238BDSP g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2248BDSP g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2258BDSP g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2268BDSP g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ݗ. DSP48E2_inst * C ݗ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2278BDSP g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2288BDSP g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2298BDSP g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2308BDSP g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2318BDSP g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ɛ. DSP48E2_inst * C ɛ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2328BDSP g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Ŝ. DSP48E2_inst * C Ŝ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2338BDSP g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2348BDSP g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2358BDSP g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ֞. DSP48E2_inst * C ֞.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2368BDSP g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ҟ. DSP48E2_inst * C ҟ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2378BDSP g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Ǡ. DSP48E2_inst * C Ǡ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2388BDSP g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2398BDSP g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2408BDSP g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ߢ. DSP48E2_inst * C ߢ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2418BDSP g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ԣ. DSP48E2_inst * C ԣ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2428BDSP g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2438BDSP g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2448BDSP g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2458BDSP g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2468BDSP g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2478BDSP g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2488BDSP g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2498BDSP g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2508BDSP g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2518BDSP g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2528BDSP g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2538BDSP g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2548BDSP g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2558BDSP g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2568BDSP g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2578BDSP g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2588BDSP g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Ű. DSP48E2_inst * C Ű.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2598BDSP g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2608BDSP g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2618BDSP g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2628BDSP g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ҳ. DSP48E2_inst * C ҳ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2638BDSP g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2648BDSP g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2658BDSP g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2668BDSP g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ߶. DSP48E2_inst * C ߶.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2678BDSP g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2688BDSP g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2698BDSP g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2708BDSP g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2718BDSP g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ˺. DSP48E2_inst * C ˺.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2728BDSP g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ǻ. DSP48E2_inst * C ǻ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2738BDSP g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2748BDSP g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2758BDSP g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ؽ. DSP48E2_inst * C ؽ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2768BDSP g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Ծ. DSP48E2_inst * C Ծ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2778BDSP g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ɿ. DSP48E2_inst * C ɿ.* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2788BDSP g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2798BDSP g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2808BDSP g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2818BDSP g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2828BDSP g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2838BDSP g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2848BDSP g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2858BDSP g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2868BDSP g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2878BDSP g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2888BDSP g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2898BDSP g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2908BDSP g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2918BDSP g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2928BDSP g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2938BDSP g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2948BDSP g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2958BDSP g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2968BDSP g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2978BDSP g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2988BDSP g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#2998BDSP g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3008BDSP g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3018BDSP g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3028BDSP g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3038BDSP g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3048BDSP g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3058BDSP g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3068BDSP g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3078BDSP g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3088BDSP g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3098BDSP g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3108BDSP g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3118BDSP g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3128BDSP g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3138BDSP g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3148BDSP g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3158BDSP g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3168BDSP g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3178BDSP g_clock_rate_din[32].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[32].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[32].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[32].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3188BDSP g_clock_rate_din[32].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[32].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[32].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[32].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3198BDSP g_clock_rate_din[32].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[32].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[32].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[32].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3208BDSP g_clock_rate_din[32].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[32].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[32].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[32].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3218BDSP g_clock_rate_din[33].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[33].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[33].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[33].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3228BDSP g_clock_rate_din[33].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[33].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[33].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[33].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3238BDSP g_clock_rate_din[33].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[33].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[33].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[33].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3248BDSP g_clock_rate_din[33].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[33].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[33].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[33].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3258BDSP g_clock_rate_din[34].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[34].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[34].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[34].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3268BDSP g_clock_rate_din[34].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[34].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[34].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[34].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3278BDSP g_clock_rate_din[34].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[34].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[34].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[34].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3288BDSP g_clock_rate_din[34].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[34].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[34].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[34].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3298BDSP g_clock_rate_din[35].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[35].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[35].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[35].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3308BDSP g_clock_rate_din[35].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[35].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[35].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[35].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3318BDSP g_clock_rate_din[35].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[35].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[35].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[35].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3328BDSP g_clock_rate_din[35].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[35].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[35].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[35].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3338BDSP g_clock_rate_din[36].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[36].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[36].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[36].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3348BDSP g_clock_rate_din[36].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[36].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[36].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[36].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3358BDSP g_clock_rate_din[36].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[36].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[36].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[36].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3368BDSP g_clock_rate_din[36].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[36].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[36].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[36].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3378BDSP g_clock_rate_din[37].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[37].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[37].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[37].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3388BDSP g_clock_rate_din[37].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[37].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[37].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[37].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3398BDSP g_clock_rate_din[37].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[37].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[37].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[37].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3408BDSP g_clock_rate_din[37].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[37].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[37].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[37].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3418BDSP g_clock_rate_din[38].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[38].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[38].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[38].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3428BDSP g_clock_rate_din[38].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[38].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[38].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[38].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3438BDSP g_clock_rate_din[38].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[38].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[38].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[38].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3448BDSP g_clock_rate_din[38].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[38].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[38].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[38].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3458BDSP g_clock_rate_din[39].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[39].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[39].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[39].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3468BDSP g_clock_rate_din[39].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[39].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[39].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[39].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3478BDSP g_clock_rate_din[39].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[39].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[39].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[39].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3488BDSP g_clock_rate_din[39].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[39].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[39].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[39].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3498BDSP g_clock_rate_din[3].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[3].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[3].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[3].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3508BDSP g_clock_rate_din[3].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[3].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[3].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[3].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3518BDSP g_clock_rate_din[3].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[3].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[3].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[3].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3528BDSP g_clock_rate_din[3].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[3].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[3].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[3].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3538BDSP g_clock_rate_din[40].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[40].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[40].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[40].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3548BDSP g_clock_rate_din[40].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[40].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[40].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[40].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3558BDSP g_clock_rate_din[40].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[40].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[40].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[40].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3568BDSP g_clock_rate_din[40].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[40].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[40].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[40].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3578BDSP g_clock_rate_din[41].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[41].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[41].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[41].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3588BDSP g_clock_rate_din[41].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[41].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[41].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[41].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3598BDSP g_clock_rate_din[41].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[41].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[41].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[41].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3608BDSP g_clock_rate_din[41].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[41].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[41].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[41].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. . DSP48E2_inst * C .* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3618BDSP g_clock_rate_din[42].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[42].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[42].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[42].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ڀ/ DSP48E2_inst * C ڀ/* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3628BDSP g_clock_rate_din[42].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[42].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[42].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[42].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3638BDSP g_clock_rate_din[42].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[42].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[42].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[42].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3648BDSP g_clock_rate_din[42].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[42].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[42].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[42].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3658BDSP g_clock_rate_din[43].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[43].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[43].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[43].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3668BDSP g_clock_rate_din[43].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[43].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[43].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[43].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3678BDSP g_clock_rate_din[43].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[43].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[43].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[43].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3688BDSP g_clock_rate_din[43].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[43].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[43].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[43].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3698BDSP g_clock_rate_din[44].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[44].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[44].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[44].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3708BDSP g_clock_rate_din[44].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[44].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[44].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[44].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3718BDSP g_clock_rate_din[44].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[44].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[44].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[44].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3728BDSP g_clock_rate_din[44].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[44].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[44].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[44].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3738BDSP g_clock_rate_din[45].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[45].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[45].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[45].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3748BDSP g_clock_rate_din[45].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[45].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[45].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[45].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3758BDSP g_clock_rate_din[45].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[45].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[45].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[45].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3768BDSP g_clock_rate_din[45].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[45].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[45].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[45].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3778BDSP g_clock_rate_din[46].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[46].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[46].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[46].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3788BDSP g_clock_rate_din[46].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[46].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[46].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[46].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ˍ/ DSP48E2_inst * C ˍ/* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3798BDSP g_clock_rate_din[46].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[46].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[46].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[46].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3808BDSP g_clock_rate_din[46].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[46].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[46].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[46].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3818BDSP g_clock_rate_din[47].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[47].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[47].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[47].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3828BDSP g_clock_rate_din[47].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[47].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[47].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[47].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ؐ/ DSP48E2_inst * C ؐ/* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3838BDSP g_clock_rate_din[47].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[47].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[47].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[47].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3848BDSP g_clock_rate_din[47].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[47].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[47].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[47].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3858BDSP g_clock_rate_din[4].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[4].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[4].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[4].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3868BDSP g_clock_rate_din[4].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[4].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[4].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[4].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3878BDSP g_clock_rate_din[4].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[4].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[4].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[4].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Ĕ/ DSP48E2_inst * C Ĕ/* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3888BDSP g_clock_rate_din[4].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[4].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[4].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[4].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3898BDSP g_clock_rate_din[5].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[5].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[5].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[5].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3908BDSP g_clock_rate_din[5].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[5].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[5].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[5].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3918BDSP g_clock_rate_din[5].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[5].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[5].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[5].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ї/ DSP48E2_inst * C ї/* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3928BDSP g_clock_rate_din[5].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[5].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[5].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[5].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ͘/ DSP48E2_inst * C ͘/* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3938BDSP g_clock_rate_din[6].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[6].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[6].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[6].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ™/ DSP48E2_inst * C ™/* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3948BDSP g_clock_rate_din[6].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[6].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[6].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[6].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3958BDSP g_clock_rate_din[6].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[6].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[6].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[6].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ޚ/ DSP48E2_inst * C ޚ/* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3968BDSP g_clock_rate_din[6].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[6].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[6].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[6].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ڛ/ DSP48E2_inst * C ڛ/* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3978BDSP g_clock_rate_din[7].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[7].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[7].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[7].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Ϝ/ DSP48E2_inst * C Ϝ/* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3988BDSP g_clock_rate_din[7].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[7].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[7].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[7].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#3998BDSP g_clock_rate_din[7].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[7].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[7].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[7].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4008BDSP g_clock_rate_din[7].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[7].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[7].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[7].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4018BDSP g_clock_rate_din[8].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[8].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[8].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[8].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ܟ/ DSP48E2_inst * C ܟ/* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4028BDSP g_clock_rate_din[8].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[8].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[8].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[8].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4038BDSP g_clock_rate_din[8].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[8].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[8].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[8].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4048BDSP g_clock_rate_din[8].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[8].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[8].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[8].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4058BDSP g_clock_rate_din[9].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[9].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[9].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[9].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4068BDSP g_clock_rate_din[9].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[9].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[9].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[9].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4078BDSP g_clock_rate_din[9].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[9].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[9].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[9].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4088BDSP g_clock_rate_din[9].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[9].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP g_clock_rate_din[9].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[9].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. / DSP48E2_inst * C /* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4098BDSP stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. 9 DSP48E2_inst * +B 9* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4108BDSP stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. 9 DSP48E2_inst * C 9* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4118BDSP stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ҥ: DSP48E2_inst * +B ҥ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4128BDSP stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ҥ: DSP48E2_inst * C ҥ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4138BDSP stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ٥: DSP48E2_inst * +B ٥:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4148BDSP stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ٥: DSP48E2_inst * C ٥:* DSP48E2_instEWarning"DPIP-2*Input pipelining2 DPIP-2#4158BDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instEWarning"DPIP-2*Input pipelining2 DPIP-2#4168BDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instDWarning"DPIP-2*Input pipelining2 DPIP-2#4178BDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instEWarning"DPIP-2*Input pipelining2 DPIP-2#4188BDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instEWarning"DPIP-2*Input pipelining2 DPIP-2#4198BDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instDWarning"DPIP-2*Input pipelining2 DPIP-2#4208BDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instEWarning"DPIP-2*Input pipelining2 DPIP-2#4218BDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instEWarning"DPIP-2*Input pipelining2 DPIP-2#4228BDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instDWarning"DPIP-2*Input pipelining2 DPIP-2#4238BDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4248BDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4258BDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4268BDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instEWarning"DPIP-2*Input pipelining2 DPIP-2#4278BDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instEWarning"DPIP-2*Input pipelining2 DPIP-2#4288BDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instDWarning"DPIP-2*Input pipelining2 DPIP-2#4298BDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instEWarning"DPIP-2*Input pipelining2 DPIP-2#4308BDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instEWarning"DPIP-2*Input pipelining2 DPIP-2#4318BDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instDWarning"DPIP-2*Input pipelining2 DPIP-2#4328BDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instEWarning"DPIP-2*Input pipelining2 DPIP-2#4338BDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instEWarning"DPIP-2*Input pipelining2 DPIP-2#4348BDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instDWarning"DPIP-2*Input pipelining2 DPIP-2#4358BDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4368BDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4378BDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4388BDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#4398BDSP stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#4408BDSP stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4418BDSP stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#4428BDSP stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#4438BDSP stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4448BDSP stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#4458BDSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#4468BDSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4478BDSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#4488BDSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#4498BDSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4508BDSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4518BDSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ک: DSP48E2_inst * +A ک:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4528BDSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ک: DSP48E2_inst * +B ک:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4538BDSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ک: DSP48E2_inst * C ک:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4548BDSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4558BDSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4568BDSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4578BDSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ̪: DSP48E2_inst * +A ̪:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4588BDSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ̪: DSP48E2_inst * +B ̪:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4598BDSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ̪: DSP48E2_inst * C ̪:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4608BDSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4618BDSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4628BDSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4638BDSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4648BDSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4658BDSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4668BDSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4678BDSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4688BDSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4698BDSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4708BDSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4718BDSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4728BDSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4738BDSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4748BDSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4758BDSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4768BDSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4778BDSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4788BDSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ۭ: DSP48E2_inst * +A ۭ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4798BDSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ۭ: DSP48E2_inst * +B ۭ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4808BDSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ۭ: DSP48E2_inst * C ۭ:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#4818BDSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#4828BDSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#4838BDSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4848BDSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ͮ: DSP48E2_inst * +A ͮ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4858BDSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ͮ: DSP48E2_inst * +B ͮ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4868BDSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ͮ: DSP48E2_inst * C ͮ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4878BDSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4888BDSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4898BDSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4908BDSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4918BDSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4928BDSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4938BDSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4948BDSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4958BDSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4968BDSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4978BDSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4988BDSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#4998BDSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5008BDSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5018BDSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5028BDSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5038BDSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5048BDSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5058BDSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ܱ: DSP48E2_inst * +A ܱ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5068BDSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ܱ: DSP48E2_inst * +B ܱ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5078BDSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ܱ: DSP48E2_inst * C ܱ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5088BDSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5098BDSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5108BDSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5118BDSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. β: DSP48E2_inst * +A β:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5128BDSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. β: DSP48E2_inst * +B β:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5138BDSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. β: DSP48E2_inst * C β:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5148BDSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5158BDSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5168BDSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5178BDSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5188BDSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5198BDSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5208BDSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5218BDSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5228BDSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5238BDSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5248BDSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5258BDSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5268BDSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5278BDSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5288BDSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5298BDSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5308BDSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5318BDSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5328BDSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ݵ: DSP48E2_inst * +A ݵ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5338BDSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ݵ: DSP48E2_inst * +B ݵ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5348BDSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ݵ: DSP48E2_inst * C ݵ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5358BDSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5368BDSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5378BDSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5388BDSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ϶: DSP48E2_inst * +A ϶:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5398BDSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ϶: DSP48E2_inst * +B ϶:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5408BDSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ϶: DSP48E2_inst * C ϶:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5418BDSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5428BDSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5438BDSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5448BDSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5458BDSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5468BDSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5478BDSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5488BDSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5498BDSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5508BDSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5518BDSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5528BDSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5538BDSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5548BDSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5558BDSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5568BDSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5578BDSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5588BDSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5598BDSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ޹: DSP48E2_inst * +A ޹:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5608BDSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ޹: DSP48E2_inst * +B ޹:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5618BDSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ޹: DSP48E2_inst * C ޹:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5628BDSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5638BDSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5648BDSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5658BDSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. к: DSP48E2_inst * +A к:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5668BDSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. к: DSP48E2_inst * +B к:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#5678BDSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. к: DSP48E2_inst * C к:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5688BDSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5698BDSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5708BDSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5718BDSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. »: DSP48E2_inst * +A »:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5728BDSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. »: DSP48E2_inst * +B »:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5738BDSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. »: DSP48E2_inst * C »:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5748BDSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5758BDSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5768BDSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5778BDSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5788BDSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5798BDSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5808BDSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5818BDSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5828BDSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5838BDSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5848BDSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5858BDSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5868BDSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ߽: DSP48E2_inst * +A ߽:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5878BDSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ߽: DSP48E2_inst * +B ߽:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5888BDSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ߽: DSP48E2_inst * C ߽:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5898BDSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5908BDSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5918BDSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5928BDSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Ѿ: DSP48E2_inst * +A Ѿ:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5938BDSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Ѿ: DSP48E2_inst * +B Ѿ:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5948BDSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Ѿ: DSP48E2_inst * C Ѿ:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5958BDSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5968BDSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5978BDSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5988BDSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. ÿ: DSP48E2_inst * +A ÿ:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#5998BDSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. ÿ: DSP48E2_inst * +B ÿ:* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#6008BDSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. ÿ: DSP48E2_inst * C ÿ:* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6018BDSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6028BDSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6038BDSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6048BDSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6058BDSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6068BDSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6078BDSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6088BDSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6098BDSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6108BDSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6118BDSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6128BDSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6138BDSP stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6148BDSP stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6158BDSP stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6168BDSP stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6178BDSP stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6188BDSP stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6198BDSP stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6208BDSP stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6218BDSP stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6228BDSP stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6238BDSP stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6248BDSP stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6258BDSP stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6268BDSP stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6278BDSP stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6288BDSP stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6298BDSP stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6308BDSP stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6318BDSP stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6328BDSP stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#6338BDSP stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6348BDSP stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6358BDSP stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6368BDSP stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6378BDSP stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6388BDSP stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6398BDSP stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6408BDSP stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6418BDSP stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6428BDSP stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6438BDSP stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6448BDSP stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6458BDSP stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6468BDSP stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6478BDSP stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6488BDSP stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6498BDSP stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6508BDSP stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6518BDSP stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6528BDSP stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6538BDSP stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6548BDSP stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6558BDSP stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6568BDSP stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6578BDSP stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6588BDSP stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6598BDSP stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6608BDSP stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6618BDSP stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6628BDSP stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6638BDSP stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6648BDSP stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6658BDSP stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#6668BDSP stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6678BDSP stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6688BDSP stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6698BDSP stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6708BDSP stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6718BDSP stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6728BDSP stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6738BDSP stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6748BDSP stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6758BDSP stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6768BDSP stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6778BDSP stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6788BDSP stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6798BDSP stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6808BDSP stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6818BDSP stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6828BDSP stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6838BDSP stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6848BDSP stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6858BDSP stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6868BDSP stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6878BDSP stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6888BDSP stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6898BDSP stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6908BDSP stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6918BDSP stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6928BDSP stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6938BDSP stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6948BDSP stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6958BDSP stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6968BDSP stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6978BDSP stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#6988BDSP stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#6998BDSP stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7008BDSP stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7018BDSP stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7028BDSP stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7038BDSP stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7048BDSP stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7058BDSP stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7068BDSP stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7078BDSP stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7088BDSP stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7098BDSP stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7108BDSP stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7118BDSP stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7128BDSP stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7138BDSP stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7148BDSP stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7158BDSP stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7168BDSP stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7178BDSP stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7188BDSP stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7198BDSP stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7208BDSP stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7218BDSP stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7228BDSP stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7238BDSP stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7248BDSP stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7258BDSP stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7268BDSP stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7278BDSP stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7288BDSP stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7298BDSP stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7308BDSP stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7318BDSP stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#7328BDSP stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7338BDSP stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7348BDSP stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7358BDSP stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7368BDSP stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7378BDSP stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7388BDSP stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7398BDSP stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7408BDSP stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7418BDSP stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7428BDSP stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7438BDSP stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7448BDSP stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7458BDSP stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7468BDSP stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7478BDSP stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7488BDSP stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7498BDSP stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7508BDSP stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7518BDSP stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7528BDSP stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7538BDSP stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7548BDSP stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7558BDSP stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7568BDSP stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7578BDSP stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7588BDSP stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7598BDSP stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7608BDSP stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7618BDSP stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7628BDSP stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7638BDSP stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7648BDSP stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#7658BDSP stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7668BDSP stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7678BDSP stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7688BDSP stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7698BDSP stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7708BDSP stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7718BDSP stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7728BDSP stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7738BDSP stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7748BDSP stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7758BDSP stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7768BDSP stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7778BDSP stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7788BDSP stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7798BDSP stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7808BDSP stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7818BDSP stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7828BDSP stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7838BDSP stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7848BDSP stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7858BDSP stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7868BDSP stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7878BDSP stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7888BDSP stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7898BDSP stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7908BDSP stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7918BDSP stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7928BDSP stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7938BDSP stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7948BDSP stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7958BDSP stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7968BDSP stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7978BDSP stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#7988BDSP stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#7998BDSP stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8008BDSP stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8018BDSP stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8028BDSP stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8038BDSP stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8048BDSP stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8058BDSP stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8068BDSP stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8078BDSP stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8088BDSP stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8098BDSP stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8108BDSP stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8118BDSP stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8128BDSP stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8138BDSP stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8148BDSP stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8158BDSP stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8168BDSP stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8178BDSP stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8188BDSP stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8198BDSP stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8208BDSP stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8218BDSP stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8228BDSP stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8238BDSP stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8248BDSP stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8258BDSP stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8268BDSP stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8278BDSP stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8288BDSP stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8298BDSP stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8308BDSP stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8318BDSP stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8328BDSP stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8338BDSP stat_regs_inst/g_DSP_rate[10].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[10].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[10].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[10].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8348BDSP stat_regs_inst/g_DSP_rate[11].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[11].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[11].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[11].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8358BDSP stat_regs_inst/g_DSP_rate[12].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[12].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[12].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[12].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8368BDSP stat_regs_inst/g_DSP_rate[13].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[13].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[13].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[13].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8378BDSP stat_regs_inst/g_DSP_rate[14].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[14].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[14].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[14].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8388BDSP stat_regs_inst/g_DSP_rate[15].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[15].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[15].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[15].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8398BDSP stat_regs_inst/g_DSP_rate[16].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[16].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[16].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[16].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8408BDSP stat_regs_inst/g_DSP_rate[17].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[17].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[17].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[17].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8418BDSP stat_regs_inst/g_DSP_rate[18].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[18].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[18].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[18].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8428BDSP stat_regs_inst/g_DSP_rate[19].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[19].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[19].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[19].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8438BDSP stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8448BDSP stat_regs_inst/g_DSP_rate[20].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[20].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[20].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[20].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8458BDSP stat_regs_inst/g_DSP_rate[21].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[21].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[21].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[21].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8468BDSP stat_regs_inst/g_DSP_rate[22].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[22].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[22].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[22].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8478BDSP stat_regs_inst/g_DSP_rate[23].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[23].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[23].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[23].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8488BDSP stat_regs_inst/g_DSP_rate[24].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[24].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[24].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[24].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8498BDSP stat_regs_inst/g_DSP_rate[25].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[25].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[25].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[25].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8508BDSP stat_regs_inst/g_DSP_rate[26].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[26].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[26].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[26].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8518BDSP stat_regs_inst/g_DSP_rate[27].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[27].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[27].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[27].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8528BDSP stat_regs_inst/g_DSP_rate[28].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[28].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[28].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[28].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8538BDSP stat_regs_inst/g_DSP_rate[29].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[29].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[29].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[29].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8548BDSP stat_regs_inst/g_DSP_rate[2].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[2].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[2].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[2].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8558BDSP stat_regs_inst/g_DSP_rate[30].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[30].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[30].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[30].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8568BDSP stat_regs_inst/g_DSP_rate[31].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[31].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[31].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[31].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8578BDSP stat_regs_inst/g_DSP_rate[32].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[32].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[32].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[32].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8588BDSP stat_regs_inst/g_DSP_rate[33].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[33].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[33].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[33].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8598BDSP stat_regs_inst/g_DSP_rate[34].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[34].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[34].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[34].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8608BDSP stat_regs_inst/g_DSP_rate[35].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[35].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[35].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[35].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8618BDSP stat_regs_inst/g_DSP_rate[36].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[36].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[36].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[36].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8628BDSP stat_regs_inst/g_DSP_rate[37].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[37].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[37].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[37].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8638BDSP stat_regs_inst/g_DSP_rate[38].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[38].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[38].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[38].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8648BDSP stat_regs_inst/g_DSP_rate[39].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[39].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[39].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[39].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8658BDSP stat_regs_inst/g_DSP_rate[3].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[3].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[3].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[3].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8668BDSP stat_regs_inst/g_DSP_rate[40].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[40].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[40].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[40].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8678BDSP stat_regs_inst/g_DSP_rate[41].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[41].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[41].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[41].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8688BDSP stat_regs_inst/g_DSP_rate[42].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[42].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[42].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[42].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8698BDSP stat_regs_inst/g_DSP_rate[43].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[43].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[43].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[43].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8708BDSP stat_regs_inst/g_DSP_rate[44].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[44].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[44].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[44].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8718BDSP stat_regs_inst/g_DSP_rate[45].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[45].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[45].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[45].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8728BDSP stat_regs_inst/g_DSP_rate[46].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[46].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[46].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[46].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8738BDSP stat_regs_inst/g_DSP_rate[47].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[47].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[47].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[47].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8748BDSP stat_regs_inst/g_DSP_rate[48].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[48].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[48].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[48].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8758BDSP stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8768BDSP stat_regs_inst/g_DSP_rate[4].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[4].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[4].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[4].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8778BDSP stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8788BDSP stat_regs_inst/g_DSP_rate[51].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[51].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[51].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[51].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8798BDSP stat_regs_inst/g_DSP_rate[52].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[52].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[52].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[52].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8808BDSP stat_regs_inst/g_DSP_rate[53].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[53].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[53].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[53].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8818BDSP stat_regs_inst/g_DSP_rate[54].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[54].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[54].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[54].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8828BDSP stat_regs_inst/g_DSP_rate[55].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[55].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[55].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[55].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8838BDSP stat_regs_inst/g_DSP_rate[56].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[56].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[56].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[56].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8848BDSP stat_regs_inst/g_DSP_rate[57].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[57].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[57].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[57].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8858BDSP stat_regs_inst/g_DSP_rate[58].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[58].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[58].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[58].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8868BDSP stat_regs_inst/g_DSP_rate[59].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[59].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[59].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[59].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8878BDSP stat_regs_inst/g_DSP_rate[5].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[5].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[5].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[5].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8888BDSP stat_regs_inst/g_DSP_rate[60].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[60].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[60].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[60].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8898BDSP stat_regs_inst/g_DSP_rate[61].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[61].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[61].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[61].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8908BDSP stat_regs_inst/g_DSP_rate[62].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[62].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[62].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[62].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#8918BDSP stat_regs_inst/g_DSP_rate[63].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[63].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[63].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[63].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8928BDSP stat_regs_inst/g_DSP_rate[6].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[6].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[6].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[6].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8938BDSP stat_regs_inst/g_DSP_rate[7].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[7].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[7].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[7].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8948BDSP stat_regs_inst/g_DSP_rate[8].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[8].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[8].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[8].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8958BDSP stat_regs_inst/g_DSP_rate[9].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[9].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_DSP_rate[9].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[9].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8968BDSP stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8978BDSP stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8988BDSP stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#8998BDSP stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9008BDSP stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9018BDSP stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9028BDSP stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9038BDSP stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9048BDSP stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9058BDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9068BDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9078BDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9088BDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9098BDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9108BDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9118BDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9128BDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9138BDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9148BDSP stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9158BDSP stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9168BDSP stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9178BDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9188BDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9198BDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9208BDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9218BDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9228BDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9238BDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9248BDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9258BDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9268BDSP stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9278BDSP stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9288BDSP stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9298BDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9308BDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9318BDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9328BDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9338BDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9348BDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9358BDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9368BDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9378BDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9388BDSP stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9398BDSP stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9408BDSP stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9418BDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9428BDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9438BDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9448BDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9458BDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9468BDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9478BDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9488BDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9498BDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9508BDSP stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9518BDSP stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9528BDSP stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9538BDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9548BDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9558BDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9568BDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9578BDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9588BDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9598BDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9608BDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9618BDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9628BDSP stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9638BDSP stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9648BDSP stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9658BDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9668BDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9678BDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9688BDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9698BDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9708BDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9718BDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9728BDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9738BDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9748BDSP stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9758BDSP stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9768BDSP stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9778BDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9788BDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9798BDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9808BDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9818BDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9828BDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9838BDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9848BDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9858BDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9868BDSP stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9878BDSP stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9888BDSP stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9898BDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9908BDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9918BDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9928BDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9938BDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9948BDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9958BDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst9Warning"DPIP-2*Input pipelining2 DPIP-2#9968BDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst8Warning"DPIP-2*Input pipelining2 DPIP-2#9978BDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9988BDSP stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#9998BDSP stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instWarning"DPIP-2*Input pipelining2 DPIP-2#10008BDSP stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10018BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10028BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10038BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10048BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10058BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10068BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10078BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10088BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#10098BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10108BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10118BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10128BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10138BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10148BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10158BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10168BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#10178BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10188BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10198BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10208BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10218BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10228BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10238BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10248BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#10258BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10268BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10278BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10288BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10298BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10308BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10318BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10328BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#10338BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10348BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10358BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10368BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10378BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10388BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10398BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10408BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#10418BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10428BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10438BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10448BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10458BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10468BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10478BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10488BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#10498BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10508BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10518BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10528BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10538BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10548BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10558BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10568BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10578BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10588BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10598BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10608BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#10618BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10628BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10638BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10648BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10658BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10668BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10678BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10688BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10698BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10708BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10718BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10728BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#10738BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10748BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10758BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10768BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10778BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10788BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10798BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10808BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10818BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10828BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10838BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10848BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#10858BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10868BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10878BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10888BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10898BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10908BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10918BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10928BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10938BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#10948BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10958BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#10968BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#10978BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10988BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#10998BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11008BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11018BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11028BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11038BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11048BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11058BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11068BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#11078BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#11088BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#11098BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11108BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11118BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11128BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11138BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11148BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11158BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11168BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11178BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11188BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#11198BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#11208BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#11218BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11228BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11238BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11248BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11258BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11268BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11278BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11288BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11298BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11308BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#11318BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#11328BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#11338BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11348BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11358BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11368BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11378BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11388BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11398BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11408BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11418BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11428BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#11438BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instBWarning"DPIP-2*Input pipelining2 DPIP-2#11448BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instAWarning"DPIP-2*Input pipelining2 DPIP-2#11458BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11468BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11478BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11488BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11498BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instzWarning"DPIP-2*Input pipelining2 DPIP-2#11508BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instyWarning"DPIP-2*Input pipelining2 DPIP-2#11518BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11528BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11538BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#11548BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#11558BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#11568BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#11578BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11588BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11598BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#11608BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11618BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11628BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#11638BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11648BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11658BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#11668BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#11678BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#11688BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#11698BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11708BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11718BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#11728BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11738BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11748BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#11758BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11768BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11778BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#11788BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#11798BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#11808BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#11818BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11828BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11838BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#11848BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11858BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11868BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#11878BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11888BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11898BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#11908BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#11918BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#11928BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#11938BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11948BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11958BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#11968BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11978BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#11988BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#11998BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12008BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12018BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12028BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12038BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12048BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#12058BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12068BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12078BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12088BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12098BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12108BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12118BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12128BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12138BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12148BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12158BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12168BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#12178BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12188BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12198BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12208BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12218BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12228BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12238BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12248BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12258BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12268BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12278BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12288BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#12298BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12308BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12318BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12328BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12338BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12348BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12358BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12368BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12378BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12388BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12398BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12408BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#12418BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12428BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12438BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12448BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12458BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12468BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12478BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12488BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12498BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12508BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12518BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12528BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#12538BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12548BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12558BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12568BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12578BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12588BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12598BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12608BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12618BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12628BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12638BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12648BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#12658BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12668BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12678BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12688BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12698BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12708BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12718BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12728BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#12738BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12748BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12758BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12768BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12778BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12788BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12798BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12808BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#12818BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12828BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12838BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12848BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12858BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12868BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12878BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12888BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#12898BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12908BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12918BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12928BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12938BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12948BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12958BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#12968BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#12978BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#12988BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#12998BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13008BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13018BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13028BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13038BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#13048BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#13058BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13068BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13078BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13088BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13098BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13108BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13118BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#13128BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#13138BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13148BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13158BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13168BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13178BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13188BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13198BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#13208BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#13218BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13228BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13238BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13248BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13258BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13268BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13278BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#13288BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#13298BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13308BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13318BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13328BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13338BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13348BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13358BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#13368BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#13378BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13388BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13398BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13408BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13418BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13428BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13438BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#13448BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#13458BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13468BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13478BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13488BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13498BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13508BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13518BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#13528BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#13538BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13548BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13558BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13568BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13578BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13588BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13598BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#13608BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#13618BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13628BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13638BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13648BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13658BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13668BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13678BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#13688BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#13698BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13708BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13718BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13728BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13738BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13748BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13758BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#13768BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#13778BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13788BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13798BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13808BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13818BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13828BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13838BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#13848BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#13858BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13868BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13878BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13888BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13898BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13908BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13918BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#13928BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#13938BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13948BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13958BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13968BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13978BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#13988BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#13998BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#14008BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#14018BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14028BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14038BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14048BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14058BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14068BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14078BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#14088BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#14098BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14108BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14118BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14128BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14138BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14148BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14158BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#14168BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#14178BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14188BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14198BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14208BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14218BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14228BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14238BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#14248BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#14258BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14268BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14278BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14288BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14298BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14308BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14318BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#14328BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#14338BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14348BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14358BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14368BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14378BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14388BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14398BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#14408BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#14418BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14428BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14438BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14448BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14458BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14468BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14478BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#14488BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#14498BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14508BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14518BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14528BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14538BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14548BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14558BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#14568BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#14578BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14588BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14598BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14608BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14618BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14628BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14638BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#14648BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14658BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14668BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14678BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14688BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14698BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14708BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#14718BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#14728BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14738BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14748BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14758BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14768BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14778BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14788BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#14798BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#14808BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14818BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14828BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14838BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14848BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14858BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14868BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#14878BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#14888BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14898BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14908BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14918BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14928BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14938BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14948BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#14958BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#14968BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14978BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#14988BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#14998BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#15008BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instz Warning"DPIP-2*Input pipelining2 DPIP-2#15018BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_insty Warning"DPIP-2*Input pipelining2 DPIP-2#15028BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#15038BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_instA Warning"DPIP-2*Input pipelining2 DPIP-2#15048BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_instB Warning"DPIP-2*Input pipelining2 DPIP-2#15058BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#15068BDSP stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#15078BDSP stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#15088BDSP stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#15098BDSP stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#15108BDSP stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#15118BDSP stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#15128BDSP stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#15138BDSP stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#15148BDSP stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#15158BDSP stat_regs_inst/i_DSP_cntr input stat_regs_inst/i_DSP_cntr/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_cntr input stat_regs_inst/i_DSP_cntr/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : i_DSP_cntr * +A :* i_DSP_cntr Warning"DPIP-2*Input pipelining2 DPIP-2#15168BDSP stat_regs_inst/i_DSP_cntr input stat_regs_inst/i_DSP_cntr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_cntr input stat_regs_inst/i_DSP_cntr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : i_DSP_cntr * +B :* i_DSP_cntr Warning"DPIP-2*Input pipelining2 DPIP-2#15178BDSP stat_regs_inst/i_DSP_cntr input stat_regs_inst/i_DSP_cntr/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_cntr input stat_regs_inst/i_DSP_cntr/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : i_DSP_cntr * C :* i_DSP_cntr Warning"DPIP-2*Input pipelining2 DPIP-2#15188BDSP stat_regs_inst/i_DSP_rate input stat_regs_inst/i_DSP_rate/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_rate input stat_regs_inst/i_DSP_rate/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : i_DSP_rate * +A :* i_DSP_rate Warning"DPIP-2*Input pipelining2 DPIP-2#15198BDSP stat_regs_inst/i_DSP_rate input stat_regs_inst/i_DSP_rate/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_rate input stat_regs_inst/i_DSP_rate/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : i_DSP_rate * +B :* i_DSP_rate Warning"DPIP-2*Input pipelining2 DPIP-2#15208BDSP stat_regs_inst/i_DSP_rate input stat_regs_inst/i_DSP_rate/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_DSP_rate input stat_regs_inst/i_DSP_rate/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : i_DSP_rate * C :* i_DSP_rate Warning"DPIP-2*Input pipelining2 DPIP-2#15218BDSP stat_regs_inst/i_stat_MUX_b/DSP48E2_inst input stat_regs_inst/i_stat_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_stat_MUX_b/DSP48E2_inst input stat_regs_inst/i_stat_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +A :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#15228BDSP stat_regs_inst/i_stat_MUX_b/DSP48E2_inst input stat_regs_inst/i_stat_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_stat_MUX_b/DSP48E2_inst input stat_regs_inst/i_stat_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * +B :* DSP48E2_inst Warning"DPIP-2*Input pipelining2 DPIP-2#15238BDSP stat_regs_inst/i_stat_MUX_b/DSP48E2_inst input stat_regs_inst/i_stat_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.JDSP stat_regs_inst/i_stat_MUX_b/DSP48E2_inst input stat_regs_inst/i_stat_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. : DSP48E2_inst * C :* DSP48E2_inst_Warning"DPOP-3*PREG Output pipelining2DPOP-3#18BDSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. . DSP48E2_inst * P .* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2DPOP-3#28BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. . DSP48E2_inst * P .* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2DPOP-3#38BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. . DSP48E2_inst * P .* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2DPOP-3#48BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ˏ. DSP48E2_inst * P ˏ.* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2DPOP-3#58BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ۏ. DSP48E2_inst * P ۏ.* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2DPOP-3#68BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. . DSP48E2_inst * P .* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2DPOP-3#78BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. . DSP48E2_inst * P .* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2DPOP-3#88BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. . DSP48E2_inst * P .* DSP48E2_inst Warning"DPOP-3*PREG Output pipelining2DPOP-3#98BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. . DSP48E2_inst * P .* DSP48E2_inst Warning"DPOP-3*PREG Output pipelining2 DPOP-3#108BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. . DSP48E2_inst * P .* DSP48E2_inst Warning"DPOP-3*PREG Output pipelining2 DPOP-3#118BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. . DSP48E2_inst * P .* DSP48E2_inst Warning"DPOP-3*PREG Output pipelining2 DPOP-3#128BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ː. DSP48E2_inst * P ː.* DSP48E2_inst Warning"DPOP-3*PREG Output pipelining2 DPOP-3#138BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ې. DSP48E2_inst * P ې.* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#148BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. . DSP48E2_inst * P .* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#158BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. . DSP48E2_inst * P .* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#168BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. . DSP48E2_inst * P .* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#178BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. . DSP48E2_inst * P .* DSP48E2_inst|Warning"DPOP-3*PREG Output pipelining2 DPOP-3#188BDSP stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ٥: DSP48E2_inst * P ٥:* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#198BDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#208BDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#218BDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#228BDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#238BDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#248BDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ɦ: DSP48E2_inst * P ɦ:* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#258BDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ٦: DSP48E2_inst * P ٦:* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#268BDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#278BDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#288BDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#298BDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#308BDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#318BDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_inst Warning"DPOP-3*PREG Output pipelining2 DPOP-3#328BDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ɧ: DSP48E2_inst * P ɧ:* DSP48E2_inst!Warning"DPOP-3*PREG Output pipelining2 DPOP-3#338BDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ٧: DSP48E2_inst * P ٧:* DSP48E2_inst"Warning"DPOP-3*PREG Output pipelining2 DPOP-3#348BDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_inst#Warning"DPOP-3*PREG Output pipelining2 DPOP-3#358BDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_inst$Warning"DPOP-3*PREG Output pipelining2 DPOP-3#368BDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_inst%Warning"DPOP-3*PREG Output pipelining2 DPOP-3#378BDSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_inst&Warning"DPOP-3*PREG Output pipelining2 DPOP-3#388BDSP stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_inst'Warning"DPOP-3*PREG Output pipelining2 DPOP-3#398BDSP stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Ǩ: DSP48E2_inst * P Ǩ:* DSP48E2_inst(Warning"DPOP-3*PREG Output pipelining2 DPOP-3#408BDSP stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ٨: DSP48E2_inst * P ٨:* DSP48E2_inst)Warning"DPOP-3*PREG Output pipelining2 DPOP-3#418BDSP stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_inst*Warning"DPOP-3*PREG Output pipelining2 DPOP-3#428BDSP stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_inst+Warning"DPOP-3*PREG Output pipelining2 DPOP-3#438BDSP stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_inst,Warning"DPOP-3*PREG Output pipelining2 DPOP-3#448BDSP stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_inst-Warning"DPOP-3*PREG Output pipelining2 DPOP-3#458BDSP stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_inst.Warning"DPOP-3*PREG Output pipelining2 DPOP-3#468BDSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ٩: DSP48E2_inst2 * P ٩:* DSP48E2_inst2/Warning"DPOP-3*PREG Output pipelining2 DPOP-3#478BDSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst20Warning"DPOP-3*PREG Output pipelining2 DPOP-3#488BDSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ˪: DSP48E2_inst2 * P ˪:* DSP48E2_inst21Warning"DPOP-3*PREG Output pipelining2 DPOP-3#498BDSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst22Warning"DPOP-3*PREG Output pipelining2 DPOP-3#508BDSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst23Warning"DPOP-3*PREG Output pipelining2 DPOP-3#518BDSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst24Warning"DPOP-3*PREG Output pipelining2 DPOP-3#528BDSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst25Warning"DPOP-3*PREG Output pipelining2 DPOP-3#538BDSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst26Warning"DPOP-3*PREG Output pipelining2 DPOP-3#548BDSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst27Warning"DPOP-3*PREG Output pipelining2 DPOP-3#558BDSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ڭ: DSP48E2_inst2 * P ڭ:* DSP48E2_inst28Warning"DPOP-3*PREG Output pipelining2 DPOP-3#568BDSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst29Warning"DPOP-3*PREG Output pipelining2 DPOP-3#578BDSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ̮: DSP48E2_inst2 * P ̮:* DSP48E2_inst2:Warning"DPOP-3*PREG Output pipelining2 DPOP-3#588BDSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2;Warning"DPOP-3*PREG Output pipelining2 DPOP-3#598BDSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2<Warning"DPOP-3*PREG Output pipelining2 DPOP-3#608BDSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2=Warning"DPOP-3*PREG Output pipelining2 DPOP-3#618BDSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2>Warning"DPOP-3*PREG Output pipelining2 DPOP-3#628BDSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2?Warning"DPOP-3*PREG Output pipelining2 DPOP-3#638BDSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2@Warning"DPOP-3*PREG Output pipelining2 DPOP-3#648BDSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ۱: DSP48E2_inst2 * P ۱:* DSP48E2_inst2AWarning"DPOP-3*PREG Output pipelining2 DPOP-3#658BDSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2BWarning"DPOP-3*PREG Output pipelining2 DPOP-3#668BDSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Ͳ: DSP48E2_inst2 * P Ͳ:* DSP48E2_inst2CWarning"DPOP-3*PREG Output pipelining2 DPOP-3#678BDSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2DWarning"DPOP-3*PREG Output pipelining2 DPOP-3#688BDSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2EWarning"DPOP-3*PREG Output pipelining2 DPOP-3#698BDSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2FWarning"DPOP-3*PREG Output pipelining2 DPOP-3#708BDSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2GWarning"DPOP-3*PREG Output pipelining2 DPOP-3#718BDSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2HWarning"DPOP-3*PREG Output pipelining2 DPOP-3#728BDSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2IWarning"DPOP-3*PREG Output pipelining2 DPOP-3#738BDSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ܵ: DSP48E2_inst2 * P ܵ:* DSP48E2_inst2JWarning"DPOP-3*PREG Output pipelining2 DPOP-3#748BDSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2KWarning"DPOP-3*PREG Output pipelining2 DPOP-3#758BDSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ζ: DSP48E2_inst2 * P ζ:* DSP48E2_inst2LWarning"DPOP-3*PREG Output pipelining2 DPOP-3#768BDSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2MWarning"DPOP-3*PREG Output pipelining2 DPOP-3#778BDSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2NWarning"DPOP-3*PREG Output pipelining2 DPOP-3#788BDSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2OWarning"DPOP-3*PREG Output pipelining2 DPOP-3#798BDSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2PWarning"DPOP-3*PREG Output pipelining2 DPOP-3#808BDSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2QWarning"DPOP-3*PREG Output pipelining2 DPOP-3#818BDSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2RWarning"DPOP-3*PREG Output pipelining2 DPOP-3#828BDSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ݹ: DSP48E2_inst2 * P ݹ:* DSP48E2_inst2SWarning"DPOP-3*PREG Output pipelining2 DPOP-3#838BDSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2TWarning"DPOP-3*PREG Output pipelining2 DPOP-3#848BDSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Ϻ: DSP48E2_inst2 * P Ϻ:* DSP48E2_inst2UWarning"DPOP-3*PREG Output pipelining2 DPOP-3#858BDSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2VWarning"DPOP-3*PREG Output pipelining2 DPOP-3#868BDSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2WWarning"DPOP-3*PREG Output pipelining2 DPOP-3#878BDSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2XWarning"DPOP-3*PREG Output pipelining2 DPOP-3#888BDSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2YWarning"DPOP-3*PREG Output pipelining2 DPOP-3#898BDSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2ZWarning"DPOP-3*PREG Output pipelining2 DPOP-3#908BDSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2[Warning"DPOP-3*PREG Output pipelining2 DPOP-3#918BDSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ޽: DSP48E2_inst2 * P ޽:* DSP48E2_inst2\Warning"DPOP-3*PREG Output pipelining2 DPOP-3#928BDSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2]Warning"DPOP-3*PREG Output pipelining2 DPOP-3#938BDSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. о: DSP48E2_inst2 * P о:* DSP48E2_inst2^Warning"DPOP-3*PREG Output pipelining2 DPOP-3#948BDSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2_Warning"DPOP-3*PREG Output pipelining2 DPOP-3#958BDSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. ¿: DSP48E2_inst2 * P ¿:* DSP48E2_inst2`Warning"DPOP-3*PREG Output pipelining2 DPOP-3#968BDSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2aWarning"DPOP-3*PREG Output pipelining2 DPOP-3#978BDSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2bWarning"DPOP-3*PREG Output pipelining2 DPOP-3#988BDSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2cWarning"DPOP-3*PREG Output pipelining2 DPOP-3#998BDSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2dWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1008BDSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2eWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1018BDSP stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2fWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1028BDSP stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2gWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1038BDSP stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2hWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1048BDSP stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2iWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1058BDSP stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2jWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1068BDSP stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2kWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1078BDSP stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2lWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1088BDSP stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2mWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1098BDSP stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2nWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1108BDSP stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2oWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1118BDSP stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2pWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1128BDSP stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2qWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1138BDSP stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2rWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1148BDSP stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2sWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1158BDSP stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2tWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1168BDSP stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2uWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1178BDSP stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2vWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1188BDSP stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2wWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1198BDSP stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2xWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1208BDSP stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2yWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1218BDSP stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2zWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1228BDSP stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2{Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1238BDSP stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2|Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1248BDSP stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2}Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1258BDSP stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2~Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1268BDSP stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1278BDSP stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1288BDSP stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1298BDSP stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1308BDSP stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1318BDSP stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1328BDSP stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1338BDSP stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1348BDSP stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1358BDSP stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1368BDSP stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1378BDSP stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1388BDSP stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1398BDSP stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1408BDSP stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1418BDSP stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1428BDSP stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1438BDSP stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1448BDSP stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1458BDSP stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1468BDSP stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1478BDSP stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1488BDSP stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1498BDSP stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1508BDSP stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1518BDSP stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1528BDSP stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1538BDSP stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1548BDSP stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1558BDSP stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1568BDSP stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1578BDSP stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1588BDSP stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1598BDSP stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1608BDSP stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1618BDSP stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1628BDSP stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1638BDSP stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1648BDSP stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1658BDSP stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1668BDSP stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1678BDSP stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1688BDSP stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1698BDSP stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1708BDSP stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1718BDSP stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1728BDSP stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2Warning"DPOP-3*PREG Output pipelining2 DPOP-3#1738BDSP stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst2 * P :* DSP48E2_inst2vWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1748BDSP stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1758BDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1768BDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1778BDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1788BDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1798BDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1808BDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1818BDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1828BDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1838BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1848BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1858BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1868BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1878BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1888BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1898BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1908BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1918BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1928BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1938BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1948BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1958BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1968BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1978BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1988BDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#1998BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2008BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2018BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2028BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2038BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2048BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2058BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2068BDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2078BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2088BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2098BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2108BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2118BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2128BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2138BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2148BDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2158BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2168BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2178BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2188BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2198BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2208BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2218BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2228BDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2238BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2248BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2258BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2268BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2278BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2288BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2298BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2308BDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2318BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2328BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2338BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2348BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2358BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2368BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2378BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2388BDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2398BDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2408BDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2418BDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2428BDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2438BDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2448BDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2458BDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2468BDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instNWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2478BDSP stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst output stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst output stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : DSP48E2_inst * P :* DSP48E2_instWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2488BDSP stat_regs_inst/i_DSP_cntr output stat_regs_inst/i_DSP_cntr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/i_DSP_cntr output stat_regs_inst/i_DSP_cntr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : i_DSP_cntr * P :* i_DSP_cntrWarning"DPOP-3*PREG Output pipelining2 DPOP-3#2498BDSP stat_regs_inst/i_DSP_rate output stat_regs_inst/i_DSP_rate/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.JDSP stat_regs_inst/i_DSP_rate output stat_regs_inst/i_DSP_rate/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. : i_DSP_rate * P :* i_DSP_rate:Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#18BThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *;Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#28BThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *;Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#38BThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *;Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#48BThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *;Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#58BThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *;Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#68BThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *;Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#78BThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *QWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#88BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *Q Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#98BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#108BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *@ Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#118BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *T Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#128BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *T Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#138BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#148BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *BWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#158BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#168BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Ï. DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#178BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Ǐ. DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#188BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ˏ. DSP48E2_inst *BWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#198BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Ϗ. DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#208BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ӏ. DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#218BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ׏. DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#228BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ۏ. DSP48E2_inst *BWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#238BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ߏ. DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#248BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#258BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#268BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *BWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#278BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#288BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#298BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#308BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *BWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#318BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *T Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#328BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *T!Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#338BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *T"Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#348BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *B#Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#358BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R$Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#368BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R%Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#378BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R&Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#388BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *@'Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#398BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R(Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#408BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R)Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#418BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R*Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#428BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *@+Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#438BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R,Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#448BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R-Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#458BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R.Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#468BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *@/Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#478BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R0Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#488BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Ð. DSP48E2_inst *R1Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#498BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ǐ. DSP48E2_inst *R2Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#508BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ː. DSP48E2_inst *@3Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#518BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ϐ. DSP48E2_inst *R4Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#528BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Ӑ. DSP48E2_inst *R5Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#538BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 א. DSP48E2_inst *R6Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#548BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ې. DSP48E2_inst *@7Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#558BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ߐ. DSP48E2_inst *R8Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#568BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R9Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#578BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R:Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#588BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *@;Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#598BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R<Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#608BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R=Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#618BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R>Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#628BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *@?Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#638BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *R@Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#648BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *RAWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#658BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *RBWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#668BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *@CWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#678BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *RDWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#688BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *REWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#698BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *RFWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#708BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *@GWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#718BThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst **HWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#728BThe DSP48E2 cell ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 . DSP48E2_inst *JIWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#738BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 9 DSP48E2_inst *JJWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#748BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ҥ: DSP48E2_inst *JKWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#758BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ٥: DSP48E2_inst *lLWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#768BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lMWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#778BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lNWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#788BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *ROWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#798BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lPWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#808BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lQWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#818BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lRWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#828BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *RSWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#838BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *TWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#848BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *UWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#858BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *VWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#868BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *tWWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#878BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *XWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#888BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *YWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#898BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *ZWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#908BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *t[Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#918BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *\Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#928BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *]Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#938BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *^Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#948BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *t_Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#958BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *`Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#968BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *aWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#978BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Ŧ: DSP48E2_inst *bWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#988BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ɦ: DSP48E2_inst *tcWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#998BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ͦ: DSP48E2_inst *dWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1008BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Ѧ: DSP48E2_inst *eWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1018BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 զ: DSP48E2_inst *fWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1028BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ٦: DSP48E2_inst *ugWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1038BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ݦ: DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1048BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *iWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1058BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *jWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1068BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *ukWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1078BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1088BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *mWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1098BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *nWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1108BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *uoWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1118BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *pWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1128BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *qWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1138BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1148BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *usWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1158BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *tWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1168BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *uWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1178BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *vWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1188BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *uwWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1198BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *xWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1208BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *yWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1218BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *zWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1228BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *u{Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1238BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *|Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1248BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *}Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1258BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *~Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1268BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *uWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1278BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1288BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1298BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ŧ: DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1308BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ɧ: DSP48E2_inst *vWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1318BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ͧ: DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1328BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ѧ: DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1338BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 է: DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1348BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ٧: DSP48E2_inst *vWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1358BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ݧ: DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1368BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1378BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1388BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *vWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1398BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1408BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1418BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1428BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *vWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1438BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1448BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1458BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1468BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *vWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1478BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *PWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1488BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *PWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1498BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *PWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1508BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1518BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1528BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1538BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *XWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1548BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[0].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[0].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1558BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1568BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ¨: DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1578BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Ǩ: DSP48E2_inst *XWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1588BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[1].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[1].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ̨: DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1598BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Ѩ: DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1608BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ը: DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1618BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ٨: DSP48E2_inst *XWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1628BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[2].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[2].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 ݨ: DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1638BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1648BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1658BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *XWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1668BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[3].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[3].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1678BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1688BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1698BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *XWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1708BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[4].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[4].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1718BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1728BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1738BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *XWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1748BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[5].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[5].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1758BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1768BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1778BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *XWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1788BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[6].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[6].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1798BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1808BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *rWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1818BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *XWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1828BThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[7].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[7].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *HWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1838BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *HWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1848BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *HWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1858BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1868BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1878BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1888BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *LWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1898BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1908BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1918BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1928BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *LWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1938BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1948BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1958BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1968BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *LWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1978BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1988BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#1998BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2008BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *LWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2018BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2028BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2038BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2048BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *LWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2058BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2068BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2078BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2088BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *LWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2098BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2108BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2118BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2128BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *LWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2138BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2148BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2158BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *hWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2168BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *LWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2178BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2188BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2198BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2208BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2218BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2228BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2238BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2248BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2258BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2268BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2278BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2288BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2298BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2308BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2318BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2328BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2338BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2348BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2358BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2368BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2378BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2388BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2398BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2408BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2418BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2428BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2438BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2448BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2458BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2468BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2478BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2488BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2498BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2508BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2518BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2528BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2538BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2548BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2558BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2568BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2578BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2588BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2598BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2608BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2618BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2628BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2638BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2648BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2658BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2668BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2678BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2688BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2698BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2708BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2718BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2728BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2738BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2748BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2758BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2768BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2778BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2788BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2798BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2808BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2818BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2828BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2838BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2848BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2858BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2868BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2878BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2888BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2898BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2908BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2918BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2928BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2938BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2948BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2958BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2968BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2978BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2988BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#2998BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3008BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3018BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3028BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3038BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3048BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3058BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3068BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3078BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3088BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3098BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3108BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3118BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3128BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3138BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3148BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3158BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3168BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3178BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3188BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3198BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3208BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3218BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3228BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3238BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3248BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3258BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3268BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3278BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3288BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3298BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3308BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3318BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3328BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3338BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3348BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3358BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3368BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3378BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3388BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3398BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3408BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3418BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3428BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3438BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3448BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3458BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3468BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3478BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3488BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3498BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3508BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3518BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3528BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3538BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3548BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3558BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3568BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3578BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3588BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3598BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3608BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3618BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3628BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3638BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3648BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3658BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3668BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3678BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3688BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3698BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3708BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3718BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3728BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3738BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3748BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3758BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3768BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3778BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3788BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3798BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3808BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3818BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3828BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3838BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3848BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3858BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3868BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3878BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3888BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3898BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3908BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3918BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3928BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3938BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3948BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3958BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3968BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3978BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3988BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#3998BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4008BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4018BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4028BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4038BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4048BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4058BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4068BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4078BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4088BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4098BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4108BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4118BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4128BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4138BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4148BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4158BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4168BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4178BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4188BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4198BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4208BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4218BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4228BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4238BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4248BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4258BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4268BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4278BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4288BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4298BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4308BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4318BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4328BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4338BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4348BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4358BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4368BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4378BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4388BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4398BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4408BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4418BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4428BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4438BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4448BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4458BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4468BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4478BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4488BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4498BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4508BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4518BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4528BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4538BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4548BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4558BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4568BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4578BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4588BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4598BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4608BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4618BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4628BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4638BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4648BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4658BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4668BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4678BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4688BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4698BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4708BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4718BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4728BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *lWarning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4738BThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *6Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4748BThe DSP48E2 cell stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *6Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4758BThe DSP48E2 cell stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *8Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4768BThe DSP48E2 cell stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *4Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4778BThe DSP48E2 cell stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *.Warning"DPREG-7*DSP48E2_PregDynOpmodeZmuxP:2 DPREG-7#4788BThe DSP48E2 cell stat_regs_inst/i_stat_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0JThe DSP48E2 cell stat_regs_inst/i_stat_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 : DSP48E2_inst *Warning" IOBUSSLRC-1*IO Bus SLR Crossings2 IOBUSSLRC-1#18BBus port GBT_refclk1_n spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 3, 1. Bits placed in SLR 0: 2, 0. JBus port GBT_refclk1_n spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 3, 1. Bits placed in SLR 0: 2, 0.  GBT_refclk1_n%STR%STR%STR%STR%STR%STR Bits placed in SLR 1: 3, 1.  Bits placed in SLR 0: 2, 0. Warning" IOBUSSLRC-1*IO Bus SLR Crossings2 IOBUSSLRC-1#28BBus port GBT_refclk1_p spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 3, 1. Bits placed in SLR 0: 2, 0. JBus port GBT_refclk1_p spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 3, 1. Bits placed in SLR 0: 2, 0.  GBT_refclk1_p%STR%STR%STR%STR%STR%STR Bits placed in SLR 1: 3, 1.  Bits placed in SLR 0: 2, 0. Warning" IOBUSSLRC-1*IO Bus SLR Crossings2 IOBUSSLRC-1#38BBus port GBT_rxn spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. JBus port GBT_rxn spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. GBT_rxn%STR%STR%STR%STR%STR%STR Bits placed in SLR 1: ^47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12.  Bits placed in SLR 0: T35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. Warning" IOBUSSLRC-1*IO Bus SLR Crossings2 IOBUSSLRC-1#48BBus port GBT_rxp spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. JBus port GBT_rxp spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. GBT_rxp%STR%STR%STR%STR%STR%STR Bits placed in SLR 1: ^47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12.  Bits placed in SLR 0: T35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. Warning" IOBUSSLRC-1*IO Bus SLR Crossings2 IOBUSSLRC-1#58BBus port GBT_txn spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. JBus port GBT_txn spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. GBT_txn%STR%STR%STR%STR%STR%STR Bits placed in SLR 1: ^47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12.  Bits placed in SLR 0: T35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. Warning" IOBUSSLRC-1*IO Bus SLR Crossings2 IOBUSSLRC-1#68BBus port GBT_txp spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. JBus port GBT_txp spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. GBT_txp%STR%STR%STR%STR%STR%STR Bits placed in SLR 1: ^47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12.  Bits placed in SLR 0: T35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. ;Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#18Bctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *<Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#28Bctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#38Bctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#48Bctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#58Bctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#68Bctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#78Bctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *RAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#88Bctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *R Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#98Bctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#108Bctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *A Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#118Bctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *U Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#128Bctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *U Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#138Bctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *UAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#148Bctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *CAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#158Bctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *UAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#168Bctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Ï. DSP48E2_inst *UAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#178Bctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Ǐ. DSP48E2_inst *UAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#188Bctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ˏ. DSP48E2_inst *CAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#198Bctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Ϗ. DSP48E2_inst *UAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#208Bctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ӏ. DSP48E2_inst *UAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#218Bctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ׏. DSP48E2_inst *UAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#228Bctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ۏ. DSP48E2_inst *CAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#238Bctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ߏ. DSP48E2_inst *UAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#248Bctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *UAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#258Bctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *UAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#268Bctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *CAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#278Bctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *UAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#288Bctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *UAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#298Bctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *UAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#308Bctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *CAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#318Bctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *U Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#328Bctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *U!Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#338Bctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *U"Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#348Bctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *C#Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#358Bctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S$Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#368Bctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S%Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#378Bctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S&Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#388Bctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *A'Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#398Bctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S(Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#408Bctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S)Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#418Bctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S*Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#428Bctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *A+Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#438Bctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S,Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#448Bctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S-Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#458Bctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S.Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#468Bctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *A/Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#478Bctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S0Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#488Bctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Ð. DSP48E2_inst *S1Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#498Bctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ǐ. DSP48E2_inst *S2Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#508Bctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ː. DSP48E2_inst *A3Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#518Bctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ϐ. DSP48E2_inst *S4Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#528Bctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Ӑ. DSP48E2_inst *S5Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#538Bctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. א. DSP48E2_inst *S6Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#548Bctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ې. DSP48E2_inst *A7Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#558Bctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ߐ. DSP48E2_inst *S8Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#568Bctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S9Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#578Bctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S:Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#588Bctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *A;Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#598Bctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S<Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#608Bctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S=Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#618Bctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S>Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#628Bctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *A?Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#638Bctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *S@Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#648Bctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *SAAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#658Bctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *SBAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#668Bctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *ACAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#678Bctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *SDAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#688Bctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *SEAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#698Bctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *SFAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#708Bctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *AGAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#718Bctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *+HAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#728Bctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *KIAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#738Bstat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. 9 DSP48E2_inst *KJAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#748Bstat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ҥ: DSP48E2_inst *KKAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#758Bstat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ٥: DSP48E2_inst *mLAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#768Bstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mMAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#778Bstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mNAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#788Bstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *SOAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#798Bstat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mPAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#808Bstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mQAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#818Bstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mRAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#828Bstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *SSAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#838Bstat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *OTAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#848Bstat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *OUAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#858Bstat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *OVAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#868Bstat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *GWAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#878Bstat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *GXAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#888Bstat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *GYAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#898Bstat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *gZAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#908Bstat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *g[Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#918Bstat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *g\Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#928Bstat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *K]Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#938Bstat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *g^Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#948Bstat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *g_Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#958Bstat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *g`Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#968Bstat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *KaAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#978Bstat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *gbAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#988Bstat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *gcAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#998Bstat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hdAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1008Bstat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *LeAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1018Bstat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hfAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1028Bstat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hgAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1038Bstat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hhAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1048Bstat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *LiAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1058Bstat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hjAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1068Bstat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hkAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1078Bstat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hlAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1088Bstat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *LmAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1098Bstat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hnAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1108Bstat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hoAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1118Bstat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hpAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1128Bstat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *LqAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1138Bstat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hrAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1148Bstat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hsAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1158Bstat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *htAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1168Bstat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *LuAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1178Bstat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hvAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1188Bstat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hwAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1198Bstat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *hxAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1208Bstat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *LyAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1218Bstat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *zAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1228Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *{Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1238Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *|Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1248Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *l}Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1258Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *~Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1268Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1278Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1288Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1298Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1308Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1318Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1328Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1338Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1348Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1358Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1368Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1378Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1388Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1398Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1408Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1418Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1428Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1438Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1448Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1458Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1468Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1478Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1488Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1498Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1508Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1518Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1528Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1538Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1548Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1558Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1568Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1578Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1588Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1598Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1608Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1618Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1628Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1638Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1648Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1658Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1668Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1678Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1688Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1698Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1708Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1718Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1728Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1738Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1748Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1758Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1768Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1778Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1788Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1798Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1808Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1818Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1828Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1838Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1848Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1858Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1868Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1878Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1888Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1898Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1908Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1918Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1928Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1938Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1948Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1958Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1968Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1978Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1988Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#1998Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2008Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2018Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2028Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2038Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2048Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2058Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2068Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2078Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2088Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2098Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2108Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2118Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2128Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2138Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2148Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2158Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2168Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2178Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2188Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2198Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2208Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2218Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2228Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2238Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2248Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2258Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2268Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2278Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2288Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2298Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2308Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2318Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2328Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2338Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2348Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2358Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2368Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2378Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2388Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2398Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2408Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2418Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2428Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2438Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2448Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2458Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2468Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2478Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2488Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2498Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2508Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2518Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2528Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2538Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2548Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2558Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2568Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2578Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2588Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2598Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2608Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2618Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2628Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2638Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2648Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2658Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2668Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2678Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2688Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2698Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2708Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2718Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2728Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2738Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2748Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2758Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2768Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2778Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2788Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2798Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2808Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2818Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2828Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2838Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2848Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2858Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2868Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2878Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2888Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2898Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2908Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2918Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2928Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2938Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2948Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2958Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2968Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2978Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2988Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#2998Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3008Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3018Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3028Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3038Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3048Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3058Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3068Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3078Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3088Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3098Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3108Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3118Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3128Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3138Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3148Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3158Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3168Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3178Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3188Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3198Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3208Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3218Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3228Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3238Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3248Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3258Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3268Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3278Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3288Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3298Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3308Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3318Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3328Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3338Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3348Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3358Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3368Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3378Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3388Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3398Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3408Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3418Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3428Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3438Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3448Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3458Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3468Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3478Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3488Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3498Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3508Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3518Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3528Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3538Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3548Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3558Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3568Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3578Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3588Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3598Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3608Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3618Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3628Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3638Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3648Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3658Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3668Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3678Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3688Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3698Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3708Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3718Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3728Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3738Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3748Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3758Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3768Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *mAdvisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3778Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *7Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3788Bstat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *7Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3798Bstat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *9Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3808Bstat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *5Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3818Bstat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst */Advisory"AVAL-155*Cenum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-155#3828Bstat_regs_inst/i_stat_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/i_stat_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *$Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#18Bctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *%Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#28Bctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *%Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#38Bctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *%Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#48Bctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *%Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#58Bctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *%Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#68Bctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *%Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#78Bctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *;Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#88Bctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *; Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#98Bctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *< Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#108Bctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst ** Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#118Bctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *> Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#128Bctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *> Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#138Bctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#148Bctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *,Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#158Bctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#168Bctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Ï. DSP48E2_inst *>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#178Bctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Ǐ. DSP48E2_inst *>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#188Bctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ˏ. DSP48E2_inst *,Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#198Bctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Ϗ. DSP48E2_inst *>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#208Bctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ӏ. DSP48E2_inst *>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#218Bctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ׏. DSP48E2_inst *>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#228Bctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ۏ. DSP48E2_inst *,Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#238Bctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ߏ. DSP48E2_inst *>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#248Bctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#258Bctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#268Bctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *,Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#278Bctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#288Bctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#298Bctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#308Bctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *,Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#318Bctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *> Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#328Bctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *>!Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#338Bctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *>"Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#348Bctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *,#Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#358Bctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<$Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#368Bctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<%Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#378Bctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<&Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#388Bctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst **'Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#398Bctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<(Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#408Bctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<)Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#418Bctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<*Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#428Bctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst **+Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#438Bctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<,Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#448Bctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<-Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#458Bctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<.Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#468Bctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst **/Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#478Bctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<0Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#488Bctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Ð. DSP48E2_inst *<1Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#498Bctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ǐ. DSP48E2_inst *<2Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#508Bctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ː. DSP48E2_inst **3Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#518Bctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ϐ. DSP48E2_inst *<4Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#528Bctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Ӑ. DSP48E2_inst *<5Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#538Bctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. א. DSP48E2_inst *<6Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#548Bctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ې. DSP48E2_inst **7Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#558Bctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ߐ. DSP48E2_inst *<8Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#568Bctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<9Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#578Bctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<:Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#588Bctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst **;Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#598Bctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<<Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#608Bctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<=Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#618Bctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<>Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#628Bctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst **?Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#638Bctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<@Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#648Bctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<AAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#658Bctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<BAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#668Bctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst **CAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#678Bctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<DAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#688Bctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<EAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#698Bctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *<FAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#708Bctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst **GAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#718Bctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *HAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#728Bctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. . DSP48E2_inst *4IAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#738Bstat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. 9 DSP48E2_inst *4JAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#748Bstat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ҥ: DSP48E2_inst *4KAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#758Bstat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. ٥: DSP48E2_inst *VLAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#768Bstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VMAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#778Bstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VNAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#788Bstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *<OAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#798Bstat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VPAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#808Bstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VQAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#818Bstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VRAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#828Bstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *<SAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#838Bstat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *8TAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#848Bstat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *8UAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#858Bstat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *8VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#868Bstat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *0WAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#878Bstat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *0XAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#888Bstat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *0YAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#898Bstat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *PZAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#908Bstat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *P[Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#918Bstat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *P\Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#928Bstat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *4]Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#938Bstat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *P^Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#948Bstat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *P_Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#958Bstat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *P`Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#968Bstat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *4aAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#978Bstat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *PbAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#988Bstat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *PcAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#998Bstat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QdAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1008Bstat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *5eAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1018Bstat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QfAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1028Bstat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QgAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1038Bstat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QhAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1048Bstat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *5iAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1058Bstat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QjAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1068Bstat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QkAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1078Bstat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QlAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1088Bstat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *5mAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1098Bstat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QnAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1108Bstat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QoAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1118Bstat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QpAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1128Bstat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *5qAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1138Bstat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QrAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1148Bstat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QsAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1158Bstat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QtAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1168Bstat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *5uAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1178Bstat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QvAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1188Bstat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QwAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1198Bstat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *QxAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1208Bstat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *5yAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1218Bstat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *qzAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1228Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *q{Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1238Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *q|Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1248Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *U}Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1258Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *q~Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1268Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *qAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1278Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1288Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1298Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1308Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1318Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1328Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1338Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1348Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1358Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1368Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1378Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1388Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1398Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1408Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1418Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1428Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1438Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1448Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1458Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1468Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1478Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1488Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1498Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1508Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1518Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1528Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1538Bstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1548Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1558Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1568Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1578Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1588Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1598Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1608Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1618Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1628Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1638Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1648Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1658Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1668Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1678Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1688Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1698Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1708Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1718Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1728Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1738Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1748Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1758Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1768Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1778Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1788Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1798Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1808Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1818Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1828Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1838Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1848Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1858Bstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1868Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1878Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1888Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1898Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1908Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1918Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1928Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1938Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1948Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1958Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1968Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1978Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1988Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#1998Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2008Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2018Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2028Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2038Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2048Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2058Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2068Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2078Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2088Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2098Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2108Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2118Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2128Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2138Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2148Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2158Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2168Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2178Bstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2188Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2198Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2208Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2218Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2228Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2238Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2248Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2258Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2268Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2278Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2288Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2298Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2308Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2318Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2328Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2338Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2348Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2358Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2368Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2378Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2388Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2398Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2408Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2418Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2428Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2438Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2448Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2458Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2468Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2478Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2488Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2498Bstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2508Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2518Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2528Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2538Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2548Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2558Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2568Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2578Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2588Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2598Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2608Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2618Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2628Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2638Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2648Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2658Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2668Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2678Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2688Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2698Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2708Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2718Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2728Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2738Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2748Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2758Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2768Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2778Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2788Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2798Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2808Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2818Bstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2828Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2838Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2848Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2858Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2868Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2878Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2888Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2898Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2908Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2918Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2928Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2938Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2948Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2958Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2968Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2978Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2988Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#2998Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3008Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3018Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3028Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3038Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3048Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3058Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3068Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3078Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3088Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3098Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3108Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3118Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3128Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3138Bstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3148Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3158Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3168Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3178Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3188Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3198Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3208Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3218Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3228Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3238Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3248Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3258Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3268Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3278Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3288Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3298Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3308Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3318Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3328Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3338Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3348Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3358Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3368Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3378Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3388Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3398Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3408Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3418Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3428Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3438Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3448Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3458Bstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3468Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3478Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3488Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3498Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3508Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3518Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3528Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3538Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3548Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3558Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3568Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3578Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3588Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3598Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3608Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3618Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3628Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3638Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3648Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3658Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3668Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3678Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3688Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3698Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3708Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3718Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3728Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3738Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3748Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3758Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *rAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3768Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *VAdvisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3778Bstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst * Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3788Bstat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst * Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3798Bstat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *"Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3808Bstat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3818Bstat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *Advisory"AVAL-156*@enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND2 AVAL-156#3828Bstat_regs_inst/i_stat_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.Jstat_regs_inst/i_stat_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. : DSP48E2_inst *vAdvisory" REQP-1669*/enum_AREG_0_connects_CEA1_GND_connects_CEA2_GND2 REQP-1669#18Bstat_regs_inst/i_DSP_cntr: When DSP48E2 attribute AREG is set to 0, the CEA1 and CEA2 pins should be tied to GND to save power.Jstat_regs_inst/i_DSP_cntr: When DSP48E2 attribute AREG is set to 0, the CEA1 and CEA2 pins should be tied to GND to save power. : i_DSP_cntr *vAdvisory" REQP-1669*/enum_AREG_0_connects_CEA1_GND_connects_CEA2_GND2 REQP-1669#28Bstat_regs_inst/i_DSP_rate: When DSP48E2 attribute AREG is set to 0, the CEA1 and CEA2 pins should be tied to GND to save power.Jstat_regs_inst/i_DSP_rate: When DSP48E2 attribute AREG is set to 0, the CEA1 and CEA2 pins should be tied to GND to save power. : i_DSP_rate *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#18Bstat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ٩: DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#28Bstat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#38Bstat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ˪: DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#48Bstat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#58Bstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#68Bstat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#78Bstat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#88Bstat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 * Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#98Bstat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 * Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#108Bstat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ڭ: DSP48E2_inst2 * Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#118Bstat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 * Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#128Bstat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ̮: DSP48E2_inst2 * Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#138Bstat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#148Bstat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#158Bstat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#168Bstat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#178Bstat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#188Bstat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#198Bstat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ۱: DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#208Bstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#218Bstat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Ͳ: DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#228Bstat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#238Bstat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#248Bstat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#258Bstat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#268Bstat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#278Bstat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#288Bstat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ܵ: DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#298Bstat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#308Bstat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ζ: DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#318Bstat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 * Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#328Bstat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *!Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#338Bstat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *"Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#348Bstat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *#Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#358Bstat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *$Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#368Bstat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *%Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#378Bstat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ݹ: DSP48E2_inst2 *&Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#388Bstat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *'Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#398Bstat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Ϻ: DSP48E2_inst2 *(Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#408Bstat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *)Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#418Bstat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 **Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#428Bstat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *+Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#438Bstat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *,Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#448Bstat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *-Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#458Bstat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *.Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#468Bstat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ޽: DSP48E2_inst2 */Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#478Bstat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *0Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#488Bstat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. о: DSP48E2_inst2 *1Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#498Bstat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *2Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#508Bstat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ¿: DSP48E2_inst2 *3Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#518Bstat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *4Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#528Bstat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *5Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#538Bstat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *6Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#548Bstat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *7Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#558Bstat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *8Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#568Bstat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *9Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#578Bstat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *:Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#588Bstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *;Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#598Bstat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *<Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#608Bstat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *=Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#618Bstat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *>Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#628Bstat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *?Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#638Bstat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *@Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#648Bstat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *AAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#658Bstat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *BAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#668Bstat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *CAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#678Bstat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *DAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#688Bstat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *EAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#698Bstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *FAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#708Bstat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *GAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#718Bstat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *HAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#728Bstat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *IAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#738Bstat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *JAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#748Bstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *KAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#758Bstat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *LAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#768Bstat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *MAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#778Bstat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *NAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#788Bstat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *OAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#798Bstat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *PAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#808Bstat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *QAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#818Bstat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *RAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#828Bstat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *SAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#838Bstat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *TAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#848Bstat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *UAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#858Bstat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *VAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#868Bstat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *WAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#878Bstat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *XAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#888Bstat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *YAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#898Bstat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *ZAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#908Bstat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *[Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#918Bstat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *\Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#928Bstat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *]Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#938Bstat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *^Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#948Bstat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *_Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#958Bstat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *`Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#968Bstat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *aAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#978Bstat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *bAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#988Bstat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *cAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#998Bstat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *dAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1008Bstat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *eAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1018Bstat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *fAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1028Bstat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *gAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1038Bstat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *hAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1048Bstat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *iAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1058Bstat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *jAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1068Bstat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *kAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1078Bstat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *lAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1088Bstat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *mAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1098Bstat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *nAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1108Bstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *oAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1118Bstat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *pAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1128Bstat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *qAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1138Bstat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *rAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1148Bstat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *sAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1158Bstat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *tAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1168Bstat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *uAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1178Bstat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *vAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1188Bstat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *wAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1198Bstat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *xAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1208Bstat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *yAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1218Bstat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *zAdvisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1228Bstat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *{Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1238Bstat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *|Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1248Bstat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *}Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1258Bstat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *~Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1268Bstat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1278Bstat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1288Bstat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1298Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[0].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[0].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[0].DSP48E2_inst *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1308Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[10].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[10].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.$ ":g_DSP[10].DSP48E2_inst *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1318Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[1].DSP48E2_inst *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1328Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[2].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[2].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[2].DSP48E2_inst *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1338Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[3].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[3].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[3].DSP48E2_inst *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1348Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[4].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[4].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[4].DSP48E2_inst *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1358Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[5].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[5].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[5].DSP48E2_inst *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1368Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[6].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[6].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[6].DSP48E2_inst *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1378Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[7].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[7].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[7].DSP48E2_inst *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1388Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[8].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[8].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[8].DSP48E2_inst *Advisory" REQP-1671*enum_AREG_1_connects_CEA1_GND2 REQP-1671#1398Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[9].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[9].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[9].DSP48E2_inst *vAdvisory" REQP-1673*/enum_BREG_0_connects_CEB1_GND_connects_CEB2_GND2 REQP-1673#18Bstat_regs_inst/i_DSP_cntr: When DSP48E2 attribute BREG is set to 0, the CEB1 and CEB2 pins should be tied to GND to save power.Jstat_regs_inst/i_DSP_cntr: When DSP48E2 attribute BREG is set to 0, the CEB1 and CEB2 pins should be tied to GND to save power. : i_DSP_cntr *vAdvisory" REQP-1673*/enum_BREG_0_connects_CEB1_GND_connects_CEB2_GND2 REQP-1673#28Bstat_regs_inst/i_DSP_rate: When DSP48E2 attribute BREG is set to 0, the CEB1 and CEB2 pins should be tied to GND to save power.Jstat_regs_inst/i_DSP_rate: When DSP48E2 attribute BREG is set to 0, the CEB1 and CEB2 pins should be tied to GND to save power. : i_DSP_rate *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#18Bstat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ٩: DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#28Bstat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#38Bstat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ˪: DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#48Bstat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#58Bstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#68Bstat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#78Bstat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#88Bstat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 * Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#98Bstat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 * Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#108Bstat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ڭ: DSP48E2_inst2 * Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#118Bstat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 * Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#128Bstat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ̮: DSP48E2_inst2 * Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#138Bstat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#148Bstat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#158Bstat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#168Bstat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#178Bstat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#188Bstat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#198Bstat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ۱: DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#208Bstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#218Bstat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Ͳ: DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#228Bstat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#238Bstat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#248Bstat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#258Bstat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#268Bstat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#278Bstat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#288Bstat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ܵ: DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#298Bstat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#308Bstat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ζ: DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#318Bstat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 * Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#328Bstat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *!Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#338Bstat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *"Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#348Bstat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *#Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#358Bstat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *$Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#368Bstat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *%Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#378Bstat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ݹ: DSP48E2_inst2 *&Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#388Bstat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *'Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#398Bstat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Ϻ: DSP48E2_inst2 *(Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#408Bstat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *)Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#418Bstat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 **Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#428Bstat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *+Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#438Bstat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *,Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#448Bstat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *-Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#458Bstat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *.Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#468Bstat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ޽: DSP48E2_inst2 */Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#478Bstat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *0Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#488Bstat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. о: DSP48E2_inst2 *1Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#498Bstat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *2Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#508Bstat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. ¿: DSP48E2_inst2 *3Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#518Bstat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *4Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#528Bstat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *5Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#538Bstat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *6Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#548Bstat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *7Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#558Bstat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *8Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#568Bstat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *9Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#578Bstat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *:Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#588Bstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *;Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#598Bstat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *<Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#608Bstat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *=Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#618Bstat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *>Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#628Bstat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *?Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#638Bstat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *@Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#648Bstat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *AAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#658Bstat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *BAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#668Bstat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *CAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#678Bstat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *DAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#688Bstat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *EAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#698Bstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *FAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#708Bstat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *GAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#718Bstat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *HAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#728Bstat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *IAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#738Bstat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *JAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#748Bstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *KAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#758Bstat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *LAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#768Bstat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *MAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#778Bstat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *NAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#788Bstat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *OAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#798Bstat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *PAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#808Bstat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *QAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#818Bstat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *RAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#828Bstat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *SAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#838Bstat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *TAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#848Bstat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *UAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#858Bstat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *VAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#868Bstat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *WAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#878Bstat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *XAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#888Bstat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *YAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#898Bstat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *ZAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#908Bstat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *[Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#918Bstat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *\Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#928Bstat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *]Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#938Bstat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *^Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#948Bstat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *_Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#958Bstat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *`Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#968Bstat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *aAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#978Bstat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *bAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#988Bstat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *cAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#998Bstat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *dAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1008Bstat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *eAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1018Bstat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *fAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1028Bstat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *gAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1038Bstat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *hAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1048Bstat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *iAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1058Bstat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *jAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1068Bstat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *kAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1078Bstat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *lAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1088Bstat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *mAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1098Bstat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *nAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1108Bstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *oAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1118Bstat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *pAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1128Bstat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *qAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1138Bstat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *rAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1148Bstat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *sAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1158Bstat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *tAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1168Bstat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *uAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1178Bstat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *vAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1188Bstat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *wAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1198Bstat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *xAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1208Bstat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *yAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1218Bstat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *zAdvisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1228Bstat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *{Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1238Bstat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *|Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1248Bstat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *}Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1258Bstat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *~Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1268Bstat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1278Bstat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1288Bstat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. : DSP48E2_inst2 *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1298Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[0].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[0].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[0].DSP48E2_inst *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1308Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[10].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[10].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.$ ":g_DSP[10].DSP48E2_inst *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1318Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[1].DSP48E2_inst *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1328Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[2].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[2].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[2].DSP48E2_inst *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1338Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[3].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[3].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[3].DSP48E2_inst *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1348Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[4].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[4].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[4].DSP48E2_inst *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1358Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[5].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[5].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[5].DSP48E2_inst *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1368Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[6].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[6].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[6].DSP48E2_inst *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1378Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[7].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[7].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[7].DSP48E2_inst *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1388Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[8].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[8].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[8].DSP48E2_inst *Advisory" REQP-1675*enum_BREG_1_connects_CEB1_GND2 REQP-1675#1398Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[9].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[9].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1.# !:g_DSP[9].DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#18Bg_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#28Bg_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Ñ. DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#38Bg_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#48Bg_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#58Bg_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#68Bg_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Д. DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#78Bg_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#88Bg_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst * Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#98Bg_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst * Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#108Bg_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ݗ. DSP48E2_inst * Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#118Bg_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst * Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#128Bg_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst * Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#138Bg_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#148Bg_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#158Bg_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ɛ. DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#168Bg_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Ŝ. DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#178Bg_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#188Bg_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#198Bg_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ֞. DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#208Bg_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ҟ. DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#218Bg_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Ǡ. DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#228Bg_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#238Bg_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#248Bg_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ߢ. DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#258Bg_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ԣ. DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#268Bg_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#278Bg_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#288Bg_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#298Bg_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#308Bg_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#318Bg_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst * Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#328Bg_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *!Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#338Bg_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *"Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#348Bg_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *#Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#358Bg_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *$Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#368Bg_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *%Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#378Bg_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *&Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#388Bg_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *'Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#398Bg_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *(Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#408Bg_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *)Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#418Bg_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst **Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#428Bg_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Ű. DSP48E2_inst *+Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#438Bg_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *,Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#448Bg_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *-Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#458Bg_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *.Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#468Bg_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ҳ. DSP48E2_inst */Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#478Bg_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *0Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#488Bg_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *1Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#498Bg_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *2Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#508Bg_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ߶. DSP48E2_inst *3Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#518Bg_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *4Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#528Bg_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *5Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#538Bg_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *6Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#548Bg_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *7Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#558Bg_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ˺. DSP48E2_inst *8Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#568Bg_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ǻ. DSP48E2_inst *9Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#578Bg_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *:Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#588Bg_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *;Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#598Bg_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ؽ. DSP48E2_inst *<Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#608Bg_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Ծ. DSP48E2_inst *=Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#618Bg_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ɿ. DSP48E2_inst *>Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#628Bg_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *?Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#638Bg_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *@Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#648Bg_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *AAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#658Bg_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *BAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#668Bg_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *CAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#678Bg_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *DAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#688Bg_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *EAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#698Bg_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *FAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#708Bg_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *GAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#718Bg_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *HAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#728Bg_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *IAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#738Bg_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *JAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#748Bg_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *KAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#758Bg_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *LAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#768Bg_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *MAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#778Bg_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *NAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#788Bg_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *OAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#798Bg_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *PAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#808Bg_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *QAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#818Bg_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *RAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#828Bg_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *SAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#838Bg_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *TAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#848Bg_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *UAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#858Bg_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *VAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#868Bg_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *WAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#878Bg_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *XAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#888Bg_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *YAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#898Bg_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *ZAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#908Bg_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *[Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#918Bg_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *\Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#928Bg_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *]Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#938Bg_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *^Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#948Bg_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *_Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#958Bg_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *`Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#968Bg_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *aAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#978Bg_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *bAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#988Bg_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *cAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#998Bg_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *dAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1008Bg_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *eAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1018Bg_clock_rate_din[32].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[32].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *fAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1028Bg_clock_rate_din[32].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[32].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *gAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1038Bg_clock_rate_din[32].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[32].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *hAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1048Bg_clock_rate_din[32].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[32].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *iAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1058Bg_clock_rate_din[33].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[33].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *jAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1068Bg_clock_rate_din[33].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[33].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *kAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1078Bg_clock_rate_din[33].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[33].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *lAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1088Bg_clock_rate_din[33].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[33].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *mAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1098Bg_clock_rate_din[34].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[34].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *nAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1108Bg_clock_rate_din[34].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[34].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *oAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1118Bg_clock_rate_din[34].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[34].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *pAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1128Bg_clock_rate_din[34].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[34].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *qAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1138Bg_clock_rate_din[35].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[35].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *rAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1148Bg_clock_rate_din[35].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[35].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *sAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1158Bg_clock_rate_din[35].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[35].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *tAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1168Bg_clock_rate_din[35].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[35].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *uAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1178Bg_clock_rate_din[36].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[36].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *vAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1188Bg_clock_rate_din[36].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[36].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *wAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1198Bg_clock_rate_din[36].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[36].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *xAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1208Bg_clock_rate_din[36].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[36].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *yAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1218Bg_clock_rate_din[37].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[37].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *zAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1228Bg_clock_rate_din[37].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[37].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *{Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1238Bg_clock_rate_din[37].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[37].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *|Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1248Bg_clock_rate_din[37].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[37].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *}Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1258Bg_clock_rate_din[38].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[38].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *~Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1268Bg_clock_rate_din[38].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[38].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1278Bg_clock_rate_din[38].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[38].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1288Bg_clock_rate_din[38].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[38].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1298Bg_clock_rate_din[39].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[39].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1308Bg_clock_rate_din[39].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[39].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1318Bg_clock_rate_din[39].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[39].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1328Bg_clock_rate_din[39].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[39].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1338Bg_clock_rate_din[3].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[3].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1348Bg_clock_rate_din[3].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[3].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1358Bg_clock_rate_din[3].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[3].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1368Bg_clock_rate_din[3].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[3].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1378Bg_clock_rate_din[40].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[40].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1388Bg_clock_rate_din[40].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[40].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1398Bg_clock_rate_din[40].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[40].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1408Bg_clock_rate_din[40].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[40].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1418Bg_clock_rate_din[41].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[41].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1428Bg_clock_rate_din[41].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[41].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1438Bg_clock_rate_din[41].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[41].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1448Bg_clock_rate_din[41].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[41].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. . DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1458Bg_clock_rate_din[42].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[42].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ڀ/ DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1468Bg_clock_rate_din[42].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[42].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1478Bg_clock_rate_din[42].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[42].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1488Bg_clock_rate_din[42].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[42].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1498Bg_clock_rate_din[43].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[43].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1508Bg_clock_rate_din[43].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[43].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1518Bg_clock_rate_din[43].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[43].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1528Bg_clock_rate_din[43].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[43].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1538Bg_clock_rate_din[44].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[44].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1548Bg_clock_rate_din[44].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[44].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1558Bg_clock_rate_din[44].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[44].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1568Bg_clock_rate_din[44].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[44].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1578Bg_clock_rate_din[45].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[45].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1588Bg_clock_rate_din[45].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[45].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1598Bg_clock_rate_din[45].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[45].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1608Bg_clock_rate_din[45].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[45].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1618Bg_clock_rate_din[46].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[46].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1628Bg_clock_rate_din[46].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[46].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ˍ/ DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1638Bg_clock_rate_din[46].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[46].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1648Bg_clock_rate_din[46].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[46].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1658Bg_clock_rate_din[47].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[47].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1668Bg_clock_rate_din[47].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[47].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ؐ/ DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1678Bg_clock_rate_din[47].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[47].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1688Bg_clock_rate_din[47].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[47].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1698Bg_clock_rate_din[4].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[4].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1708Bg_clock_rate_din[4].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[4].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1718Bg_clock_rate_din[4].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[4].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Ĕ/ DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1728Bg_clock_rate_din[4].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[4].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1738Bg_clock_rate_din[5].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[5].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1748Bg_clock_rate_din[5].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[5].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1758Bg_clock_rate_din[5].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[5].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ї/ DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1768Bg_clock_rate_din[5].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[5].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ͘/ DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1778Bg_clock_rate_din[6].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[6].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ™/ DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1788Bg_clock_rate_din[6].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[6].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1798Bg_clock_rate_din[6].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[6].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ޚ/ DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1808Bg_clock_rate_din[6].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[6].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ڛ/ DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1818Bg_clock_rate_din[7].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[7].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Ϝ/ DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1828Bg_clock_rate_din[7].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[7].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1838Bg_clock_rate_din[7].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[7].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1848Bg_clock_rate_din[7].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[7].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1858Bg_clock_rate_din[8].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[8].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ܟ/ DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1868Bg_clock_rate_din[8].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[8].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1878Bg_clock_rate_din[8].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[8].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1888Bg_clock_rate_din[8].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[8].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1898Bg_clock_rate_din[9].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[9].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1908Bg_clock_rate_din[9].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[9].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1918Bg_clock_rate_din[9].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[9].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1928Bg_clock_rate_din[9].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jg_clock_rate_din[9].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. / DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1938Bstat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1948Bstat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ک: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1958Bstat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1968Bstat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ̪: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1978Bstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1988Bstat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#1998Bstat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2008Bstat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2018Bstat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2028Bstat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2038Bstat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ۭ: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2048Bstat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2058Bstat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ͮ: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2068Bstat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2078Bstat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2088Bstat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2098Bstat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2108Bstat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2118Bstat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2128Bstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ܱ: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2138Bstat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2148Bstat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. β: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2158Bstat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2168Bstat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2178Bstat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2188Bstat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2198Bstat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2208Bstat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2218Bstat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ݵ: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2228Bstat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2238Bstat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ϶: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2248Bstat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2258Bstat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2268Bstat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2278Bstat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2288Bstat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2298Bstat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2308Bstat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ޹: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2318Bstat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2328Bstat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. к: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2338Bstat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2348Bstat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. »: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2358Bstat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2368Bstat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2378Bstat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2388Bstat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2398Bstat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ߽: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2408Bstat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2418Bstat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Ѿ: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2428Bstat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2438Bstat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. ÿ: DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2448Bstat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2458Bstat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2468Bstat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2478Bstat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2488Bstat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2498Bstat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2508Bstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2518Bstat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2528Bstat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2538Bstat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2548Bstat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2558Bstat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2568Bstat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2578Bstat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2588Bstat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2598Bstat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2608Bstat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2618Bstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2628Bstat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2638Bstat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2648Bstat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2658Bstat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2668Bstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2678Bstat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2688Bstat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2698Bstat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2708Bstat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2718Bstat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2728Bstat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2738Bstat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2748Bstat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2758Bstat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2768Bstat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2778Bstat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2788Bstat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2798Bstat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2808Bstat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2818Bstat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2828Bstat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2838Bstat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2848Bstat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2858Bstat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2868Bstat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2878Bstat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2888Bstat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2898Bstat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2908Bstat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2918Bstat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2928Bstat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2938Bstat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2948Bstat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2958Bstat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2968Bstat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2978Bstat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2988Bstat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#2998Bstat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3008Bstat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3018Bstat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3028Bstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3038Bstat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3048Bstat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3058Bstat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3068Bstat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3078Bstat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3088Bstat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3098Bstat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3108Bstat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3118Bstat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3128Bstat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3138Bstat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3148Bstat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3158Bstat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3168Bstat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3178Bstat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3188Bstat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3198Bstat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3208Bstat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3218Bstat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3228Bstat_regs_inst/g_DSP_rate[10].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[10].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3238Bstat_regs_inst/g_DSP_rate[11].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[11].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3248Bstat_regs_inst/g_DSP_rate[12].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[12].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3258Bstat_regs_inst/g_DSP_rate[13].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[13].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3268Bstat_regs_inst/g_DSP_rate[14].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[14].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3278Bstat_regs_inst/g_DSP_rate[15].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[15].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3288Bstat_regs_inst/g_DSP_rate[16].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[16].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3298Bstat_regs_inst/g_DSP_rate[17].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[17].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3308Bstat_regs_inst/g_DSP_rate[18].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[18].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3318Bstat_regs_inst/g_DSP_rate[19].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[19].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3328Bstat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3338Bstat_regs_inst/g_DSP_rate[20].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[20].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3348Bstat_regs_inst/g_DSP_rate[21].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[21].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3358Bstat_regs_inst/g_DSP_rate[22].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[22].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3368Bstat_regs_inst/g_DSP_rate[23].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[23].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3378Bstat_regs_inst/g_DSP_rate[24].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[24].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3388Bstat_regs_inst/g_DSP_rate[25].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[25].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3398Bstat_regs_inst/g_DSP_rate[26].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[26].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3408Bstat_regs_inst/g_DSP_rate[27].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[27].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3418Bstat_regs_inst/g_DSP_rate[28].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[28].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3428Bstat_regs_inst/g_DSP_rate[29].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[29].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3438Bstat_regs_inst/g_DSP_rate[2].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[2].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3448Bstat_regs_inst/g_DSP_rate[30].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[30].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3458Bstat_regs_inst/g_DSP_rate[31].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[31].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3468Bstat_regs_inst/g_DSP_rate[32].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[32].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3478Bstat_regs_inst/g_DSP_rate[33].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[33].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3488Bstat_regs_inst/g_DSP_rate[34].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[34].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3498Bstat_regs_inst/g_DSP_rate[35].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[35].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3508Bstat_regs_inst/g_DSP_rate[36].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[36].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3518Bstat_regs_inst/g_DSP_rate[37].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[37].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3528Bstat_regs_inst/g_DSP_rate[38].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[38].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3538Bstat_regs_inst/g_DSP_rate[39].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[39].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3548Bstat_regs_inst/g_DSP_rate[3].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[3].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3558Bstat_regs_inst/g_DSP_rate[40].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[40].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3568Bstat_regs_inst/g_DSP_rate[41].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[41].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3578Bstat_regs_inst/g_DSP_rate[42].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[42].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3588Bstat_regs_inst/g_DSP_rate[43].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[43].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3598Bstat_regs_inst/g_DSP_rate[44].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[44].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3608Bstat_regs_inst/g_DSP_rate[45].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[45].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3618Bstat_regs_inst/g_DSP_rate[46].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[46].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3628Bstat_regs_inst/g_DSP_rate[47].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[47].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3638Bstat_regs_inst/g_DSP_rate[48].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[48].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3648Bstat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3658Bstat_regs_inst/g_DSP_rate[4].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[4].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3668Bstat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3678Bstat_regs_inst/g_DSP_rate[51].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[51].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3688Bstat_regs_inst/g_DSP_rate[52].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[52].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3698Bstat_regs_inst/g_DSP_rate[53].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[53].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3708Bstat_regs_inst/g_DSP_rate[54].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[54].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3718Bstat_regs_inst/g_DSP_rate[55].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[55].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3728Bstat_regs_inst/g_DSP_rate[56].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[56].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3738Bstat_regs_inst/g_DSP_rate[57].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[57].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3748Bstat_regs_inst/g_DSP_rate[58].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[58].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3758Bstat_regs_inst/g_DSP_rate[59].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[59].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3768Bstat_regs_inst/g_DSP_rate[5].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[5].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3778Bstat_regs_inst/g_DSP_rate[60].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[60].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3788Bstat_regs_inst/g_DSP_rate[61].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[61].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3798Bstat_regs_inst/g_DSP_rate[62].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[62].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3808Bstat_regs_inst/g_DSP_rate[63].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[63].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3818Bstat_regs_inst/g_DSP_rate[6].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[6].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3828Bstat_regs_inst/g_DSP_rate[7].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[7].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3838Bstat_regs_inst/g_DSP_rate[8].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[8].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *Advisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3848Bstat_regs_inst/g_DSP_rate[9].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_rate[9].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : DSP48E2_inst *dAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3858B~stat_regs_inst/i_DSP_cntr: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.J~stat_regs_inst/i_DSP_cntr: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : i_DSP_cntr *dAdvisory" REQP-1678*enum_CREG_0_connects_CEC_GND2 REQP-1678#3868B~stat_regs_inst/i_DSP_rate: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power.J~stat_regs_inst/i_DSP_rate: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. : i_DSP_rate *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#18Bstat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. ٩: DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#28Bstat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#38Bstat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. ˪: DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#48Bstat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#58Bstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#68Bstat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#78Bstat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#88Bstat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 * Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#98Bstat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 * Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#108Bstat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. ڭ: DSP48E2_inst2 * Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#118Bstat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 * Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#128Bstat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. ̮: DSP48E2_inst2 * Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#138Bstat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#148Bstat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#158Bstat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#168Bstat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#178Bstat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#188Bstat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#198Bstat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. ۱: DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#208Bstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#218Bstat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Ͳ: DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#228Bstat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#238Bstat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#248Bstat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#258Bstat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#268Bstat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#278Bstat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#288Bstat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. ܵ: DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#298Bstat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#308Bstat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. ζ: DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#318Bstat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 * Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#328Bstat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *!Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#338Bstat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *"Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#348Bstat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *#Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#358Bstat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *$Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#368Bstat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *%Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#378Bstat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. ݹ: DSP48E2_inst2 *&Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#388Bstat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *'Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#398Bstat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Ϻ: DSP48E2_inst2 *(Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#408Bstat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *)Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#418Bstat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 **Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#428Bstat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *+Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#438Bstat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *,Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#448Bstat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *-Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#458Bstat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *.Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#468Bstat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. ޽: DSP48E2_inst2 */Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#478Bstat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *0Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#488Bstat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. о: DSP48E2_inst2 *1Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#498Bstat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *2Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#508Bstat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. ¿: DSP48E2_inst2 *3Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#518Bstat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *4Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#528Bstat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *5Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#538Bstat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *6Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#548Bstat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *7Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#558Bstat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *8Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#568Bstat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *9Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#578Bstat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *:Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#588Bstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *;Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#598Bstat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *<Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#608Bstat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *=Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#618Bstat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *>Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#628Bstat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *?Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#638Bstat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *@Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#648Bstat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *AAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#658Bstat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *BAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#668Bstat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *CAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#678Bstat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *DAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#688Bstat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *EAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#698Bstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *FAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#708Bstat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *GAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#718Bstat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *HAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#728Bstat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *IAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#738Bstat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *JAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#748Bstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *KAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#758Bstat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *LAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#768Bstat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *MAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#778Bstat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *NAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#788Bstat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *OAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#798Bstat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *PAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#808Bstat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *QAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#818Bstat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *RAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#828Bstat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *SAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#838Bstat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *TAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#848Bstat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *UAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#858Bstat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *VAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#868Bstat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *WAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#878Bstat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *XAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#888Bstat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *YAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#898Bstat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *ZAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#908Bstat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *[Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#918Bstat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *\Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#928Bstat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *]Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#938Bstat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *^Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#948Bstat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *_Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#958Bstat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *`Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#968Bstat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *aAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#978Bstat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *bAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#988Bstat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *cAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#998Bstat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *dAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1008Bstat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *eAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1018Bstat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *fAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1028Bstat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *gAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1038Bstat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *hAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1048Bstat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *iAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1058Bstat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *jAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1068Bstat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *kAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1078Bstat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *lAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1088Bstat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *mAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1098Bstat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *nAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1108Bstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *oAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1118Bstat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *pAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1128Bstat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *qAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1138Bstat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *rAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1148Bstat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *sAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1158Bstat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *tAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1168Bstat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *uAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1178Bstat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *vAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1188Bstat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *wAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1198Bstat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *xAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1208Bstat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *yAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1218Bstat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *zAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1228Bstat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *{Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1238Bstat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *|Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1248Bstat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *}Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1258Bstat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *~Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1268Bstat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1278Bstat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *Advisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1288Bstat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.Jstat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : DSP48E2_inst2 *dAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1298B~stat_regs_inst/i_DSP_cntr: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.J~stat_regs_inst/i_DSP_cntr: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : i_DSP_cntr *dAdvisory" REQP-1680*enum_PREG_0_connects_CEP_GND2 REQP-1680#1308B~stat_regs_inst/i_DSP_rate: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power.J~stat_regs_inst/i_DSP_rate: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. : i_DSP_rate *Advisory" REQP-1681*with_OPMODE_USE_MULT_NONE2 REQP-1681#18Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[0].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[0].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.# !:g_DSP[0].DSP48E2_inst *Advisory" REQP-1681*with_OPMODE_USE_MULT_NONE2 REQP-1681#28Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[10].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[10].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.$ ":g_DSP[10].DSP48E2_inst *Advisory" REQP-1681*with_OPMODE_USE_MULT_NONE2 REQP-1681#38Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.# !:g_DSP[1].DSP48E2_inst *Advisory" REQP-1681*with_OPMODE_USE_MULT_NONE2 REQP-1681#48Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[2].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[2].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.# !:g_DSP[2].DSP48E2_inst *Advisory" REQP-1681*with_OPMODE_USE_MULT_NONE2 REQP-1681#58Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[3].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[3].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.# !:g_DSP[3].DSP48E2_inst *Advisory" REQP-1681*with_OPMODE_USE_MULT_NONE2 REQP-1681#68Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[4].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[4].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.# !:g_DSP[4].DSP48E2_inst *Advisory" REQP-1681*with_OPMODE_USE_MULT_NONE2 REQP-1681#78Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[5].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[5].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.# !:g_DSP[5].DSP48E2_inst *Advisory" REQP-1681*with_OPMODE_USE_MULT_NONE2 REQP-1681#88Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[6].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[6].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.# !:g_DSP[6].DSP48E2_inst * Advisory" REQP-1681*with_OPMODE_USE_MULT_NONE2 REQP-1681#98Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[7].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[7].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.# !:g_DSP[7].DSP48E2_inst * Advisory" REQP-1681*with_OPMODE_USE_MULT_NONE2 REQP-1681#108Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[8].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[8].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.# !:g_DSP[8].DSP48E2_inst * Advisory" REQP-1681*with_OPMODE_USE_MULT_NONE2 REQP-1681#118Bstat_regs_inst/i_cntr_rst_ctrl/g_DSP[9].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.Jstat_regs_inst/i_cntr_rst_ctrl/g_DSP[9].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE.# !:g_DSP[9].DSP48E2_inst *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#18BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.- +h gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#28BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.- +j gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#38BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.- +l gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#48BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.- +n gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#58BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.- +o gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#68BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.- +q gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#78BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.- +s gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#88BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.- +u gen_wr_a.gen_word_narrow.mem_reg * Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#98BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.- +w gen_wr_a.gen_word_narrow.mem_reg * Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#108BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.- +y gen_wr_a.gen_word_narrow.mem_reg * Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#118BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.- +{ gen_wr_a.gen_word_narrow.mem_reg * Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#128BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.- +} gen_wr_a.gen_word_narrow.mem_reg * Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#138BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.- + gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#148BSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Á gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#158BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#168BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#178BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#188BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#198BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#208BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#218BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#228BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#238BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#248BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#258BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#268BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#278BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#288BSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#298BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#308BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#318BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg * Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#328BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *!Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#338BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *"Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#348BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *#Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#358BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *$Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#368BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *%Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#378BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *&Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#388BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *'Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#398BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *(Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#408BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *)Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#418BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg **Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#428BSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *+Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#438BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *,Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#448BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *-Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#458BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *.Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#468BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg */Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#478BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *0Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#488BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *1Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#498BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *2Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#508BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *3Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#518BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *4Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#528BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *5Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#538BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *6Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#548BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *7Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#558BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *8Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#568BSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *9Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#578BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *:Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#588BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *;Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#598BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *<Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#608BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *=Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#618BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *>Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#628BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *?Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#638BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *@Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#648BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *AAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#658BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *BAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#668BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *CAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#678BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *DAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#688BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *EAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#698BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *FAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#708BSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *GAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#718BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *HAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#728BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *IAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#738BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *JAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#748BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *KAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#758BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *LAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#768BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *MAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#778BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *NAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#788BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *OAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#798BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *PAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#808BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *QAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#818BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *RAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#828BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *SAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#838BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *TAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#848BSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *UAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#858BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *VAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#868BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *WAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#878BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *XAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#888BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *YAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#898BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *ZAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#908BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *[Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#918BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *\Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#928BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *]Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#938BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *^Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#948BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *_Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#958BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *`Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#968BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *aAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#978BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *bAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#988BSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *cAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#998BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *dAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1008BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *eAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1018BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *fAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1028BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *gAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1038BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *hAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1048BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *iAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1058BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *jAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1068BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *kAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1078BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *lAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1088BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *mAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1098BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *nAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1108BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *oAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1118BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *pAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1128BSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *qAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1138BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *rAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1148BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *sAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1158BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *tAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1168BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *uAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1178BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *vAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1188BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *wAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1198BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *xAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1208BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *yAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1218BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *zAdvisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1228BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *{Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1238BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *|Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1248BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *}Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1258BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *~Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1268BSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1278BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1288BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1298BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1308BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1318BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1328BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1338BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1348BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1358BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ܷ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1368BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ӹ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1378BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ʻ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1388BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1398BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1408BSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1418BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1428BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1438BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1448BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1458BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1468BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1478BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1488BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,خ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1498BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ϰ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1508BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ʋ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1518BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1528BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1538BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1548BSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,º  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1558BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1568BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1578BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ݞ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1588BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ԡ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1598BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1608BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ݣ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1618BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ԥ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1628BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,˧  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1638BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,©  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1648BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1658BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1668BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1678BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1688BSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1698BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1708BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ە  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1718BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,җ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1728BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ə  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1738BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ؚ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1748BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ҝ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1758BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ɞ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1768BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1778BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1788BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1798BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1808BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1818BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1828BSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1838BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ٌ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1848BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ύ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1858BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ő  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1868BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1878BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,˓  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1888BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ŕ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1898BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1908BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1918BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1928BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1938BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1948BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1958BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1968BSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1978BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,̅ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1988BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#1998BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2008BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2018BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2028BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2038BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2048BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2058BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2068BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2078BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2088BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2098BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2108BSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2118BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2128BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2138BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2148BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2158BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2168BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2178BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2188BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2198BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2208BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2218BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2228BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2238BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2248BSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2258BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2268BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2278BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2288BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2298BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2308BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2318BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2328BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2338BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2348BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2358BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2368BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2378BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2388BSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2398BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2408BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2418BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2428BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2438BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2448BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2458BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2468BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2478BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2488BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2498BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2508BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2518BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,چ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2528BSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2538BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2548BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2558BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2568BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2578BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2588BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2598BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2608BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2618BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2628BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2638BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2648BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2658BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2668BSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2678BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2688BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2698BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2708BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2718BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2728BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2738BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2748BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2758BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2768BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2778BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2788BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2798BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2808BSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2818BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2828BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2838BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2848BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2858BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2868BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2878BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2888BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2898BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2908BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2918BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2928BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2938BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2948BSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2958BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2968BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2978BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2988BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#2998BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3008BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3018BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3028BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3038BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3048BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3058BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3068BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3078BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3088BSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3098BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3108BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3118BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3128BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3138BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3148BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3158BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3168BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3178BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3188BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3198BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3208BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3218BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3228BSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3238BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3248BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3258BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3268BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3278BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3288BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3298BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3308BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3318BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3328BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3338BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3348BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3358BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3368BSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3378BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,޾ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3388BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3398BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3408BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3418BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3428BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3438BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3448BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3458BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3468BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3478BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3488BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3498BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3508BSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3518BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ӷ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3528BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ȹ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3538BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3548BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3558BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ž gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3568BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3578BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3588BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3598BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3608BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3618BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3628BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3638BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3648BSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3658BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ư gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3668BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3678BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3688BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3698BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3708BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3718BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3728BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3738BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3748BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3758BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3768BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3778BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3788BSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3798BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3808BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3818BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3828BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3838BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3848BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3858BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3868BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3878BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3888BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3898BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3908BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3918BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3928BSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3938BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3948BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3958BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3968BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3978BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3988BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#3998BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4008BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4018BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4028BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4038BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4048BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4058BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,޸ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4068BSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4078BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4088BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4098BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4108BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4118BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4128BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4138BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4148BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4158BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4168BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4178BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4188BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ܯ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4198BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ӱ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4208BSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4218BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4228BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4238BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4248BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4258BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4268BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4278BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4288BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4298BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4308BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4318BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ڦ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4328BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ѩ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4338BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ȫ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4348BSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,߬ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4358BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4368BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4378BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4388BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4398BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4408BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4418BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4428BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4438BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ߛ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4448BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,֝ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4458BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,͟ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4468BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ġ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4478BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4488BSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ҥ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4498BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4508BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4518BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4528BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4538BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4548BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4558BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4568BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ݒ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4578BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ԕ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4588BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,˖ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4598BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,˜ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4608BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4618BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4628BSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ǟ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4638BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. , gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4648BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4658BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4668BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ل  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4678BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4688BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4698BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ى  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4708BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ћ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4718BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ǎ  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4728BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4738BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4748BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4758BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4768BSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4778BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4788BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4798BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4808BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4818BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,  gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4828BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Հ! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4838BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,̂! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4848BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ä! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4858BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4868BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4878BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4888BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4898BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4908BSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4918BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4928BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4938BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4948BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4958BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4968BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4978BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4988BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#4998BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,! gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5008BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5018BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5028BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5038BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5048BSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5058BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5068BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5078BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5088BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5098BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5108BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5118BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5128BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5138BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5148BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5158BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5168BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5178BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ," gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5188BSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5198BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5208BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5218BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5228BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5238BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5248BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5258BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5268BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5278BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5288BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5298BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5308BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5318BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5328BSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,# gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5338BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5348BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5358BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5368BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5378BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5388BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5398BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5408BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5418BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5428BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5438BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5448BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5458BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5468BSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,$ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5478BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5488BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5498BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5508BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5518BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5528BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5538BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5548BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5558BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5568BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5578BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5588BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5598BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5608BSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,% gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5618BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5628BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5638BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5648BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5658BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5668BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5678BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5688BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5698BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5708BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5718BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5728BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5738BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5748BSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,& gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5758BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5768BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5778BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5788BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5798BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5808BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5818BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5828BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5838BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5848BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5858BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5868BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5878BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5888BSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,' gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5898BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5908BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5918BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5928BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5938BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5948BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5958BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5968BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5978BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5988BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#5998BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6008BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6018BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6028BSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,( gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6038BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6048BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6058BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6068BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6078BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6088BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6098BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6108BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6118BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6128BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6138BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6148BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6158BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6168BSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,) gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6178BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6188BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6198BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,޴* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6208BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ն* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6218BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6228BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,޹* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6238BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ջ* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6248BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,̽* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6258BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ÿ* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6268BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6278BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6288BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6298BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6308BSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,* gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6318BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6328BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ܫ+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6338BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ӭ+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6348BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ʯ+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6358BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ٰ+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6368BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ӳ+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6378BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ʴ+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6388BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6398BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6408BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6418BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6428BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6438BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6448BSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,+ gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6458BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ܢ, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6468BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ѥ, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6478BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ȧ, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6488BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6498BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,Ω, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6508BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ȫ, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6518BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6528BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6538BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6548BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6558BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6568BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6578BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6588BSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,, gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6598BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ϛ- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6608BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ĝ- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6618BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6628BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6638BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6648BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6658BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6668BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6678BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6688BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6698BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6708BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6718BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6728BSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,- gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6738BSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,ǭ9 gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6748BSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,9 gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6758BSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,9 gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6768BSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,9 gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6778BSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,9 gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6788BSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,9 gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6798BSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,9 gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6808BSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,9 gen_wr_a.gen_word_narrow.mem_reg *Advisory" REQP-1934*$RAMB18E2_nochange_collision_advisory2 REQP-1934#6818BSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.JSynchronous clocking is detected for BRAM (i_I2C_if/I2C_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.. ,9 gen_wr_a.gen_word_narrow.mem_reg *